Analog Switched-Capacitor Neural Network for Low-Power In-Memory Computing
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Solution Overview
Problem
Deep Neural Networks (DNNs) face significant power consumption issues due to large-scale matrix-vector multiplications, which dominate energy usage in modern very large-scale integration (VLSI) technologies, primarily attributed to extensive data movement during computations.
Innovation Solution
The implementation of in-memory computing using charge-domain circuit operations with capacitors and transistors, allowing for local storage and computation of matrix elements and vector elements, reducing data movement through charge sharing among capacitors, and employing a compact circuit structure for neural networks, specifically in binarized neural networks, to minimize energy expenditure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional digital computing methods are used for matrix-vector multiplications in deep neural networks, then computational accuracy is maintained, but power consumption increases significantly due to extensive data movement
Solution Approach 1:
The patent merges memory and computation functions into a single integrated structure where matrix elements are stored in memory bit cells that directly perform computational operations. This eliminates the need for separate data movement between memory and processing units, reducing energy consumption while maintaining computational accuracy through charge-domain operations.
Solution Approach 2:
The patent replaces traditional digital mechanical data movement with charge-domain computational operations. Instead of physically moving data between memory and processor, the system uses charge sharing and capacitor-based computations to perform matrix-vector multiplications in-place, significantly reducing energy expenditure.
2Productivity
If data is moved between memory and processing units for neural network computations, then computational operations can be performed, but data movement consumes significant energy
Solution Approach 1:
The patent segments the computational system into multiple parallel memory bit cells, each capable of independent computational operations. This segmentation allows simultaneous processing of multiple data elements without requiring centralized data movement, maintaining high computational throughput while minimizing energy consumption through distributed in-memory computing.
3Loss of energy
If in-memory computing with charge-domain operations is implemented, then energy consumption is reduced, but circuit complexity increases
Solution Approach 1:
The patent implements universal memory bit cells that can perform multiple functions: data storage, computational operations, and result accumulation. This multi-functionality reduces the need for separate dedicated circuits for each operation, managing circuit complexity while enabling energy-efficient in-memory computing across the entire neural network processing pipeline.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces power consumption in neural networks by decreasing data movement and enhancing computational signal-to-noise ratio (SNR), achieving a ten to one hundred fold decrease in energy consumption compared to traditional methods.
Implementation Method 1
a plurality of capacitors configured to store a result of in-memory computing from the memory bit cells
Implementation Method 2
perform analog charge-domain computations using the input signal and the plurality of matrix values
Data Source
AI summary
Systems and methods are provided for reducing power in in-memory computing, matrix-vector computations, and neural networks. An apparatus for in-memory computing using charge-domain circuit operation includes transistors configured as memory bit cells, transistors configured to perform in-memory computing using the memory bit cells, capacitors configured to store a result of in-memory computing from the memory bit cells, and switches, wherein, based on a setting of each of the switches, the charges on at least a portion of the plurality of capacitors are shorted together. Shorting together the plurality of capacitors yields a computation result.