Switched Capacitor Pulse Timing for Systematic Offset Reduction
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Solution Overview
Problem
Switched capacitor circuits in wireless communications circuitry exhibit gain-dependent systematic offset, degrading performance.
Innovation Solution
A switched capacitor circuit design with controlled switch signals, including first and second pulse signals with specific timing, and a shared load capacitor, to mitigate charge injection and reduce systematic offset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If switched capacitor circuits are used for signal amplification in wireless communications circuitry, then signal amplification capability is improved, but gain-dependent systematic offset increases and degrades performance
Solution Approach 1:
The switched capacitor circuit is divided into multiple non-overlapping phases controlled by different pulse signals. The first pulse signal controls the first set of switches during a first time interval, while the second pulse signal controls the second set of switches during a second time interval that does not overlap with the first. This temporal segmentation eliminates simultaneous switching conflicts and reduces gain-dependent systematic offset while maintaining signal amplification capability.
2Device complexity
If conventional switched capacitor circuit design is used, then circuit simplicity is maintained, but systematic offset reduction is insufficient
Solution Approach 1:
The circuit employs periodic non-overlapping pulse signals to control different sets of switches in alternating time intervals. The first pulse signal and second pulse signal are generated periodically with distinct time intervals, creating a rhythmic switching pattern that systematically eliminates offset errors while maintaining circuit simplicity through regular periodic operation.
Data Source
AI summary
A switched capacitor circuit is provided that may include a first capacitor, a second capacitor, one or more switches coupled between the first and second capacitors, and a first output switch coupled between the first capacitor and a first output terminal. The one or more switches can be controlled by a first pulse signal, and the first output switch can be controlled by a second pulse signal different than the first pulse signal. The switched capacitor circuit can further include a second output switch coupled between the second capacitor and a second output terminal different than the first output terminal. The second output switch can also be controlled by the second pulse signal. The second pulse signal can overlap only a portion of the first pulse signal.