Switched-Capacitor RCO Calibration Without Comparators or PLLs
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Solution Overview
Problem
Comparator-based resistor-capacitor oscillators face limitations in achieving high-frequency operation due to power consumption issues, require significant IC footprint for phase locked loops, and need precise resistor-capacitor arrays for accurate frequency calibration, which consume power and space.
Innovation Solution
The proposed resistor-capacitor oscillator design employs a switched capacitor, low pass filter, reference voltage generator, voltage-controlled oscillator, frequency divider, and switched capacitor driver to generate a sawtooth or ramp voltage, filter, and integrate it to produce a frequency control signal, eliminating the need for comparators and allowing digital frequency calibration, thus achieving higher frequencies with reduced power and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If comparator-based resistor-capacitor oscillators are used to achieve accurate frequency calibration, then frequency precision is improved, but power consumption increases and IC area increases
Solution Approach 1:
The patent removes the comparator from the oscillator circuit, extracting the harmful element that causes excessive power consumption and large IC area. The frequency calibration function is then achieved through digital frequency calibration without requiring a comparator, thus resolving the contradiction between precision and power consumption.
Solution Approach 2:
The patent replaces the analog comparator-based frequency calibration mechanism with a digital frequency calibration system. This substitution eliminates the need for large resistor-capacitor arrays and comparators, reducing both power consumption and IC area while maintaining frequency calibration precision.
2Measurement precision
If phase locked loops are used for frequency calibration, then frequency precision is improved, but IC footprint increases
Solution Approach 1:
The patent extracts and removes the phase locked loop from the oscillator system, eliminating the need for large IC footprint. Frequency calibration precision is maintained through digital frequency calibration methods that do not require the complex phase locked loop architecture.
Solution Approach 2:
The patent uses digital frequency calibration as a simplified copy or alternative to the phase locked loop function. Instead of implementing the full phase locked loop mechanism, a digital calibration system replicates the frequency adjustment capability with significantly reduced hardware requirements.
3Speed
If high-frequency operation is achieved in comparator-based oscillators, then clock frequency is improved, but power consumption increases
Solution Approach 1:
The patent replaces the comparator-based high-frequency operation mechanism with a switched capacitor-based system. This substitution enables high-frequency operation with reduced power consumption by eliminating the continuous operation of comparators and using periodic switching instead.
Solution Approach 2:
The patent employs periodic switching of capacitors to achieve high-frequency operation. Instead of continuous comparator operation that consumes power, the system uses periodic charge transfer and switching actions to generate high-frequency clocks with lower power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves higher clock frequencies without the need for comparators or phase locked loops, saving power and IC area, and enables accurate digital calibration of the oscillator, suitable for low-power and high-security applications up to 500 MHz.
Implementation Method 1
a switched capacitor configured to generate a sawtooth or ramp voltage in response to a switched capacitor drive signal
Implementation Method 2
a low pass filter (LPF) configured to filter the sawtooth or ramp voltage to generate a filtered voltage
Implementation Method 3
an integrator configured to integrate a difference between the sawtooth or ramp voltage and the reference voltage to generate a frequency control signal
Implementation Method 4
a voltage controlled oscillator (VCO) configured to generate first clock based on the frequency control signal
Data Source
AI summary
An oscillator including a switched capacitor configured to generate a sawtooth or ramp voltage in response to a switched capacitor drive signal; a low pass filter (LPF) configured to filter the sawtooth or ramp voltage to generate a filtered voltage; a reference voltage generator configured to generate a reference voltage; an integrator configured to integrate a difference between the sawtooth or ramp voltage and the reference voltage to generate a frequency control signal; a voltage controlled oscillator (VCO) configured to generate a first clock based on the frequency control signal; a frequency divider configured to frequency divide the first clock to generate a second clock; and a switched capacitor driver configured to generate the switched capacitor drive signal in response to the second clock. The oscillator may also include a switched capacitor sampler to sample the sawtooth or ramp voltage, wherein the filtered voltage is based on the sampled voltage.


