Multi-Stage Switched-Capacitor Delay for Sub-Nanosecond RF Timing
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Solution Overview
Problem
Existing RF delay devices are limited by minimum delay resolution of 8/FS, which is insufficient for full duplex applications and broadband phased array applications, and lack the ability to provide programmable delays over a broad bandwidth.
Innovation Solution
A programmable delay device with an input stage using M sampling switched capacitor storage elements and a programmable delay stage with M×N delay switched capacitor storage elements, employing independent clocks for input and output reconstruction stages to achieve a minimum delay resolution of 1/FS and maximum delay of over 100 ns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single-stage switched capacitor delay device is used, then the device complexity is low, but the minimum delay resolution is limited to 8/FS which is insufficient for full duplex applications
Solution Approach 1:
The delay device is divided into multiple stages, with each stage contributing a portion of the total delay. The first stage provides coarse delay with M switched capacitor elements, while subsequent stages provide fine delay adjustments. This segmentation enables the system to achieve 1/FS delay resolution (improving measurement precision) while distributing the complexity across manageable stages rather than requiring a single complex stage (managing device complexity).
Solution Approach 2:
The patent introduces a multi-dimensional delay structure by adding temporal dimension through sequential staging. Instead of achieving all delay resolution in a single spatial stage, the delay is distributed across multiple time-sequential stages, where each stage operates at different clock phases. This dimensional transformation allows fine delay resolution without proportionally increasing the complexity of any single stage.
2Duration of action of moving object
If acoustic delay lines are used to achieve >100 ns delay, then the delay duration is sufficient, but the bandwidth is narrow and the device cannot provide programmable delay
Solution Approach 1:
The patent replaces acoustic/mechanical delay lines with an electrical switched capacitor system. The switched capacitor circuits use electronic switching and capacitive storage to achieve delay, eliminating the mechanical/acoustic limitations of narrow bandwidth and fixed delay characteristics. This substitution enables both long delay duration (>100 ns) and programmable delay capability through digital control of the switched capacitor elements.
Solution Approach 2:
The delay device incorporates dynamic control through programmable switched capacitor elements that can be selectively enabled or disabled based on digital control signals. This dynamic configuration allows the delay duration to be programmably adjusted while maintaining the ability to achieve >100 ns maximum delay. The system transitions from static acoustic delay to dynamically controllable electronic delay, providing both long duration and adaptability.
3Duration of action of stationary object
If the sampling rate at individual delay switched capacitor storage elements is high, then the bandwidth is broad, but the leakage current increases and maximum delay is limited
Solution Approach 1:
The patent employs periodic sampling action where delay switched capacitor elements are activated only during specific clock phases rather than continuously operating at full sampling rate. By periodically enabling storage elements based on their position in the delay chain, the system achieves long maximum delay (>100 ns) while reducing the effective sampling rate at individual elements. This periodic operation significantly reduces leakage current compared to continuous high-rate sampling, as each element is active only when needed for its specific delay interval.
Data Source
AI summary
A programmable delay device providing a delay resolution of less than 1 ns and a maximum delay of >100 ns over a broad bandwidth is disclosed. The device includes an input stage with M sampling switched capacitor elements, reducing the sampling rate by M. The device includes a programmable delay stage with M programmable switched capacitor banks, each bank having N delay switched capacitor storage elements. The programmable delay stage includes a total of M×N delay switched capacitor storage elements, reducing the sampling rate by M×N. This reduced sampling rate permits smaller sampling switches, with reduced leakage current and longer programmable delay times. The device includes an output reconstruction stage that reconstructs a delayed version of the input signal by combining signals from the programmable delay stage. The sampling clocks for the input and output reconstruction stages are independent, allowing a delay resolution corresponding to the sampling rate.