Switched-Capacitor Signal Conversion for Low-Power SAR ADCs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Successive-approximation register (SAR) analog-to-digital converters (ADCs) face challenges in reducing power consumption and mitigating capacitor mismatch during signal conversion, particularly due to the need for a power-hungry register to store common-mode voltage and the inefficiencies associated with capacitor mismatch in conversion cycles.
Innovation Solution
A signal conversion circuit utilizing a pair of capacitors with equal capacitance values, coupled to different reference signals instead of common-mode voltage, which reduces power consumption and mitigates capacitor mismatch by exchanging reference signals across conversion cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a register is used to store common-mode voltage in traditional SAR ADCs, then the common-mode voltage can be maintained, but power consumption increases significantly
Solution Approach 1:
The patent extracts and eliminates the power-hungry register component from the SAR ADC architecture by using a differential capacitor structure that inherently maintains common-mode voltage through its symmetric configuration, thereby removing the need for active power-consuming storage elements
Solution Approach 2:
Instead of using an active register to store and maintain common-mode voltage, the patent inverts the approach by using passive capacitive elements in a differential configuration that naturally preserve the common-mode level through charge conservation and symmetric switching operations
2Measurement precision
If capacitor mismatch occurs in conversion cycles, then conversion accuracy degrades, but traditional methods cannot effectively mitigate this mismatch
Solution Approach 1:
The patent applies asymmetry in the switching sequence and reference signal application to differential capacitors, where the first and second capacitors are switched and referenced in opposite patterns, causing systematic mismatch errors to cancel out in the differential output
Solution Approach 2:
The patent implements local quality by assigning different reference signals (first reference signal and second reference signal) to different capacitors in a controlled manner, allowing each capacitor to operate with optimized local conditions that compensate for individual mismatch characteristics
Data Source
AI summary
A signal conversion circuit includes a first pair of capacitors and a comparator. The first pair of capacitors includes a first capacitor and a second capacitor having a same capacitance value. Each of the first capacitor and the second capacitor is coupled to an input signal during a first sampling phase, while uncoupled from the input signal during a first conversion phase after the first sampling phase. The comparator has a first input terminal and a second input terminal. During the first conversion phase, the first capacitor is coupled between the first input terminal and a first reference signal, the second capacitor is coupled between the first input terminal and a second reference signal different from the first reference signal, and the comparator is configured to compare a signal level at the first input terminal and a signal level at the second input terminal to convert the input signal.