Switched Capacitor Cores Scaling for ADC Truncation

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Solution Overview

Problem

Low-precision ADC truncation in switched capacitor computation cores for neural network inference reduces accuracy due to reduced precision of analog MACC outputs, leading to decreased performance.

Innovation Solution

An auto-search algorithm and hardware implementation to determine optimal integer scalars for ADC truncation, incorporating scaling options such as amplifiers, input multipliers, and charge sharing to modify analog signals during switched-capacitor computation, ensuring accurate neural network inference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If low-precision ADC is used in switched capacitor computation cores, then device complexity and manufacturing cost are reduced, but measurement precision of analog MACC outputs deteriorates

Engineering Contradiction:
ImproveADC precisionVSAvoidanalog MACC output precision
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by determining optimal integer scalars during a training phase before actual inference. The auto-search algorithm pre-computes scaling factors that will be applied during inference to compensate for ADC truncation effects, ensuring accuracy is maintained without requiring complex real-time adjustments

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the parameter of scaling factors applied to MACC operations. By dynamically adjusting these scalar values based on the specific neural network layer and input characteristics, the system compensates for precision loss from low-precision ADC while maintaining compatibility with simplified hardware

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If ADC truncation is applied to reduce precision errors, then manufacturing precision is improved, but loss of information in analog MACC outputs increases

Engineering Contradiction:
ImproveADC truncation accuracyVSAvoidanalog MACC output information
Core Design Contradiction:
Manufacturing precisionVSLoss of information

Solution Approach 1:

The patent introduces an intermediary scaling mechanism between the analog MACC output and the ADC conversion. The optimal integer scalars act as mediators that pre-condition the analog signals to maximize the effective use of limited ADC resolution, thereby reducing information loss during the truncation process

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system implements feedback through the auto-search algorithm that determines optimal scalars based on training data characteristics. This feedback loop allows the system to learn and adapt scaling factors that minimize information loss for specific neural network workloads

Inventive Principle:
Principle #23Feedback

3Reliability

If scaling factors are applied to MACC inputs or outputs, then neural network accuracy is maintained, but device complexity increases

Engineering Contradiction:
Improveneural network accuracyVSAvoidscaling hardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by implementing scaling operations only at specific critical points in the computation pipeline - namely at the input of certain neural network layers where precision is most impactful. This selective application maintains accuracy while minimizing the overall complexity burden

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system uses simple digital scaling factors that can be replicated and applied through straightforward multiplication operations. These digital scalars are much simpler to implement than analog scaling circuits, achieving the same accuracy improvement with minimal complexity increase

Inventive Principle:
Principle #26Copying

Data Source

PatentUS20240176584A1Scalable Switch Capacitor Computation Cores for Accurate and Efficient Deep Learning Inference
Publication Date: 2024.05.30 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US20240176584A1 patent drawing
  • US20240176584A1 patent drawing
  • US20240176584A1 patent drawing

AI summary

An apparatus comprising: a first plurality of inputs representing an activation input vector; a second plurality of inputs representing a weight input vector; an analog multiplier-and-accumulator to generate a first analog voltage representing a first multiply-and-accumulate result for the said first inputs and the second inputs; a voltage multiplier that takes the said first analog voltage and produces a second analog voltage representing, a second multiply-and-accumulate result by multiplying at least one scaling factor to the first analog voltage; an analog to digital converter configured to convert the said second analog voltage multiply-and-accumulate result into a digital signal using a limited-precision operation during a neural network inference operation; and a hardware controller configured to determine the at least one scaling factor based on the first multiply-and-accumulate result, or a software controller configured to determine the at least one scaling factor based on the first multiply-and-accumulate result.