Synchronously Switched Comparator for Multi-Wire Bus Demodulation
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Solution Overview
Problem
High-speed digital interconnection systems face limitations in achieving reliable, error-free data transfer at rates beyond 20 Gbps due to data skew, inter-symbol interference, and increased complexity and power consumption, which conventional signaling methods struggle to address effectively.
Innovation Solution
The use of vector signaling codes, specifically Ensemble NRZ (ENRZ) and duobinary encoding, combined with Hadamard transforms and multi-input comparator-demodulation circuits, to create robust, high-speed communication channels over multiple wires, enabling data transfer rates of at least 50 Gigabits per second per interconnection wire while minimizing ISI and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional signaling methods are used to achieve high-speed data transfer, then data transfer rate is improved, but inter-symbol interference and data skew increase
Solution Approach 1:
The patent segments the data transfer process into multiple parallel lanes (e.g., 4-lane interface) with independent signaling paths. Each lane operates at a lower individual rate but collectively achieves high aggregate throughput, reducing inter-symbol interference in each segment while maintaining overall productivity
Solution Approach 2:
The patent transitions from single-lane high-speed signaling to multi-lane parallel signaling, adding spatial dimension to the data transfer. This dimensional change allows each lane to operate at manageable speeds while achieving high aggregate data rates through parallelism
2Productivity
If conventional signaling methods are used to increase data transfer rate, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent changes the signaling parameters by using vector signaling codes (VSC) with specific properties (e.g., constant envelope, orthogonal codes) that simplify the transmitter and receiver design. The use of Hadamard codes provides inherent orthogonality that reduces interference without requiring complex equalization algorithms
3Productivity
If conventional signaling methods are used to achieve high data transfer rates, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic clocking and synchronized switching in the multi-input comparator-demodulator circuit. The circuit operates in periodic cycles of integration and reset, allowing efficient power management through clock-gating and reducing dynamic power consumption while maintaining high-speed operation
4Productivity
If conventional signaling methods are used to increase data transfer rate, then productivity is improved, but inter-symbol interference increases
Solution Approach 1:
The patent extracts and removes the carrier signal through synchronous demodulation in the multi-input comparator-demodulator. By using reference clocks to recover and remove the carrier, the system eliminates carrier-induced interference and isolates the baseband data signals, reducing inter-symbol interference
Solution Approach 2:
The patent introduces synchronous demodulation as an intermediary process between the received modulated signal and the final data output. The demodulator acts as a mediator that converts the high-frequency carrier-modulated signals into baseband signals, filtering out inter-symbol interference in the process
Data Source
AI summary
Methods and systems are described for obtaining a set of carrier-modulated symbols of a carrier-modulated codeword, each carrier-modulated symbol received via a respective wire of a plurality of wires of a multi-wire bus, applying each carrier-modulated symbol of the set of carrier-modulated symbols to a corresponding transistor of a set of transistors, the set of transistors further connected to a pair of output nodes according to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors, recovering a demodulation signal from the carrier-modulated symbols, and generating a demodulated sub-channel data output as a differential voltage on the pair of output nodes based on a linear combination of the set of carrier-modulated symbols by controlling conductivity of the set of transistors according to the demodulation signal.