Switched-Delay Phase Frequency Detector for PLL Current Calibration
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Solution Overview
Problem
Conventional phase-locked loop (PLL) devices face challenges in maintaining synchronization due to current mismatches in the charge pump circuit, leading to static phase errors and reduced calibration resolution, which affects the performance and accuracy of the PLL system.
Innovation Solution
A phase-locked loop device with a switched-delay phase frequency detector that employs two different delay times, allowing for calibration of charge pump currents and adjusting high-level pulse widths based on synchronization states, enhancing calibration resolution and reducing static phase errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional phase frequency detector with fixed delay is used, then the circuit structure is simple, but current mismatches in the charge pump circuit cause static phase errors and reduced calibration resolution
Solution Approach 1:
The patent implements a switched-delay phase frequency detector that dynamically switches between a first delay value and a second delay value based on the synchronization state of the PLL. During calibration mode, the detector uses the second delay value to generate wider pulse widths for better current measurement resolution. During normal operation, it switches to the first delay value for standard phase detection. This dynamic adjustment of delay parameters enables high-resolution calibration without permanently increasing circuit complexity.
Solution Approach 2:
The invention changes the delay parameter of the phase frequency detector based on operational mode. By switching between different delay values (first delay and second delay), the system adapts the pulse width generation to match the calibration requirements. The second delay value produces larger pulse widths that improve the resolution of charge pump current calibration, while the first delay value maintains normal operating performance.
2Measurement precision
If the pulse widths of up signal and down signal are adjusted to compensate for current mismatches, then the static phase error is reduced, but the rising edges become misaligned causing additional phase errors
Solution Approach 1:
The patent segments the delay functionality into two distinct delay paths: a first delay path for the up signal and a second delay path for the down signal. Each path can be independently controlled with different delay values. During calibration, the system can apply different delay adjustments to each signal path to compensate for current mismatches without affecting the other path, thereby maintaining edge alignment while achieving current balance.
Solution Approach 2:
The switched-delay mechanism dynamically adjusts the delay applied to each signal path based on the operational state and calibration requirements. This dynamic control allows the system to optimize pulse widths for calibration purposes while maintaining proper edge alignment during normal operation, resolving the conflict between compensation accuracy and synchronization reliability.
Data Source
AI summary
A phase frequency detector with two different delays is disclosed herein. The phase detector comprises a first D flip-flop, a second D flip-flop, a first delay unit and a second delay unit. The first D flip-flop receives a reference signal to output an up signal. The second D flip-flop receives a clock signal to output a down signal. The first delay unit delays the received signal with a first delay. The second delay unit delays the received signal with a second delay. When the reference signal synchronizes with the clock signal and the charge pump currents are calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the first delay, and when the reference signal does not synchronize with the clock signal and the charge pump currents are not calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the second delay.