Switched Emitter Follower Circuit for Higher Sampling Frequency
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Solution Overview
Problem
Conventional switched emitter follower circuits are limited by the upper frequency of the clock signal due to parasitic resistance and capacitance, restricting the sampling frequency and hindering high-speed operation in analog-to-digital converters.
Innovation Solution
Incorporating a Gilbert-cell type multiplication circuit and additional transistors and capacitors, allowing the switched emitter follower circuit to operate at twice the clock frequency while maintaining conventional clock frequency constraints, and enhancing noise resistance through differential transistor configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional switched emitter follower circuit is used, then the circuit structure is simple, but the sampling frequency is limited by the upper frequency of the clock signal due to parasitic resistance and capacitance
Solution Approach 1:
The circuit is divided into two parallel paths: a first path with a first transistor and first capacitor for high-speed sampling, and a second path with a second transistor and second capacitor for signal buffering. This segmentation allows each path to be optimized for its specific function, enabling the overall circuit to achieve higher sampling frequencies without excessive complexity
Solution Approach 2:
The circuit achieves multi-functionality by having the first transistor path handle high-frequency sampling while the second transistor path provides signal buffering and level shifting. This allows a single circuit configuration to simultaneously achieve high sampling frequency and proper signal level matching, resolving the contradiction between performance and complexity
2Speed
If the clock frequency is increased to achieve higher sampling frequency, then the sampling speed improves, but parasitic resistance and capacitance limit the upper frequency range
Solution Approach 1:
The circuit uses dynamic switching of the first transistor based on clock signals to enable high-speed sampling only when needed, while the second transistor provides continuous signal buffering. This dynamic operation allows the circuit to achieve high sampling speeds without the parasitic effects being continuously problematic
Solution Approach 2:
The second transistor and second capacitor act as an intermediary between the high-frequency sampling node and the output, buffering the signal and isolating the parasitic effects of the first transistor path from the output stage, thereby enabling higher sampling frequencies
Data Source
AI summary
A switched emitter follower circuit is constituted by a transistor in which a base is connected to a signal input terminal, a power voltage is applied to a collector, and an emitter is connected to a signal output terminal, a capacitor in which one end is connected to the collector of the transistor, and the other end is connected to the emitter of the transistor, and a Gilbert-cell type multiplication circuit in which a positive-phase clock output terminal is connected to the emitter of the transistor, a negative-phase clock output terminal is connected to the base of the transistor, and a multiplication result of a differential clock signal and a differential clock signal input from an outside is output to the positive-phase clock output terminal and the negative-phase clock output terminal.