Half-Period Switched Frequency Divider for Low-Noise Band Coverage
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Solution Overview
Problem
The increasing number of frequency bands in wireless transceivers requires a frequency synthesiser to cover a wider frequency range, which can degrade the quality of the local oscillator signal and increase silicon area, and simple division methods like dividing by powers of two do not provide adequate frequency optimization or isolation between circuits.
Innovation Solution
A frequency divider that employs a clock signal to generate a first and second reference signal, with the second signal delayed by half a period, and switches between them once per cycle to produce an output signal with a non-integer division ratio, maintaining low noise and constant duty cycle, using a mode control stage and a divide-by-two stage for selection signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a VCO or DCO with wider tuning range is used to cover increased frequency range, then the frequency range coverage is improved, but the quality of the local oscillator signal is degraded
Solution Approach 1:
The frequency synthesizer is divided into multiple VCOs or DCOs, each with a specific tuning range. A frequency selection signal selectively activates one VCO/DCO at a time based on the desired frequency band, avoiding the need to widen the tuning range of a single oscillator and thus maintaining signal quality while covering a broad frequency range.
Solution Approach 2:
The system dynamically switches between different VCOs or DCOs based on the required frequency band. The frequency selection signal enables adaptive switching, allowing the system to optimize signal quality for each frequency band while maintaining broad coverage capability.
2Adaptability or versatility
If multiple VCOs or DCOs with different tuning ranges are used to cover increased frequency range, then the frequency range coverage is improved, but the silicon area is increased
Solution Approach 1:
Multiple VCOs or DCOs share common control and output circuits. The frequency selection signal routes the output of the active oscillator through shared buffering and frequency division stages, reducing redundant circuitry and minimizing the overall silicon area despite having multiple oscillators.
3Device complexity
If simple division by powers of two is used, then the device complexity is reduced, but the frequency optimization and isolation between circuits is insufficient
Solution Approach 1:
The frequency divider uses dynamic division ratios that can be adjusted based on the operating frequency band. The division ratio is selected from multiple possible values (not limited to powers of two) to optimize the output frequency for each band, providing both flexibility and circuit isolation while managing complexity through selective adjustment.
Data Source
AI summary
A frequency divider comprises a signal generation stage arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal. A synchronization stage is arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal.