Half-Period Switched Frequency Divider for Low-Noise Isolation
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Solution Overview
Problem
The increasing number of frequency bands in wireless transceivers requires a frequency synthesiser to cover a wider frequency range, which can degrade the quality of the local oscillator signal and increase silicon area, and existing methods for frequency division do not provide adequate isolation between circuits.
Innovation Solution
A frequency divider that generates an output signal by switching between a first and second reference signal, where the second signal is delayed by half a period of the clock signal, allowing for low complexity and low noise frequency division with a non-integer division ratio, and a synchronisation stage ensures the output signal has a constant duty cycle and is synchronised to the clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a VCO or DCO with wider tuning range is used to cover increased frequency range, then the frequency range coverage is improved, but the quality of the local oscillator signal is degraded
Solution Approach 1:
The patent divides the frequency synthesis function into multiple segments: a fixed-frequency VCO/DCO that generates high-quality oscillation, and a separate frequency division stage that provides the required frequency multiplication/division. This segmentation allows the VCO to operate at optimal frequency with high signal quality while the division stage handles frequency range requirements.
Solution Approach 2:
The patent introduces an intermediary frequency division circuit between the VCO and the frequency synthesiser output. This intermediary stage takes the high-quality VCO signal and divides it to produce the required output frequencies, thereby protecting the signal quality from degradation while achieving wide frequency coverage.
2Adaptability or versatility
If multiple VCOs or DCOs with different tuning ranges are used to cover increased frequency range, then the frequency range coverage is improved, but the silicon area is increased
Solution Approach 1:
The patent employs a single VCO/DCO that serves multiple frequency bands through frequency division. Instead of having separate VCOs for each frequency band, one universal VCO generates the base signal that is then divided to produce multiple output frequencies, making the VCO multi-functional and reducing the total component count.
Solution Approach 2:
The patent uses frequency division to create multiple output frequencies from a single VCO source. Rather than duplicating multiple VCO circuits, the system copies the frequency information through division, generating multiple frequency outputs from one master oscillator, thereby reducing silicon area.
3Speed
If a smaller gate length is employed to facilitate operation at higher frequencies, then the maximum operating frequency is improved, but the isolation between frequency synthesiser and other circuits is degraded
Solution Approach 1:
The patent introduces an intermediary frequency division stage between the high-frequency VCO and the output circuits. This division stage acts as a buffer that provides isolation, preventing the harmful effects of small gate length VCOs from directly affecting other circuits while still enabling high-frequency operation.
4Device complexity
If simple binary division is used for frequency division, then the device complexity is reduced, but the isolation between circuits is insufficient
Solution Approach 1:
The patent segments the frequency division function into multiple stages rather than using a single simple divider. This multi-stage approach maintains relatively low complexity while providing better isolation between circuits, as each division stage can be optimised for specific frequency ranges and isolation requirements.
Data Source
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AI summary
A frequency divider (100) comprises a signal generation stage (110) arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal. A synchronisation stage (120) is arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal.