Switched-Gate Operational Amplifier for Lower Input Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Operational amplifiers face challenges in reducing settling time, which affects their operational speed, particularly in applications like display drivers where multiple amplifiers are coupled to the same signal line, leading to increased input capacitance and voltage level fluctuations.
Innovation Solution
The operational amplifier design includes a configuration with transistors, constant current sources, and switches that allow for selective connection and disconnection of gates, reducing effective input capacitance by adjusting transistor gate widths and operating in specific states to minimize input capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple operational amplifiers are coupled to the same signal line, then the operational speed is improved, but the input capacitance increases causing voltage level fluctuations
Solution Approach 1:
The patent implements dynamic switching of transistor gate connections using control signals. The gates of second and third transistors are selectively connected to different nodes (input node or output node) based on operational phase, making the input capacitance dynamic rather than fixed. This allows the circuit to optimize capacitance based on operational requirements.
Solution Approach 2:
The patent changes the effective input capacitance parameter by selectively connecting transistor gates to different nodes. During certain phases, gates are connected to the input node contributing to input capacitance, while during other phases they are connected to the output node, reducing the effective input capacitance. This parameter transformation resolves the contradiction between speed and voltage stability.
2Power
If transistor gate widths are increased to improve current driving capability, then the power is improved, but the input capacitance increases
Solution Approach 1:
The patent makes the contribution of transistor gates to input capacitance dynamic by selectively connecting them to different nodes. Transistors with larger gate widths (providing higher current capability) have their gates dynamically connected to the output node during critical phases, preventing their capacitance from adding to the input node capacitance. This separates the power capability from the input capacitance penalty.
Solution Approach 2:
The output node serves as an intermediary connection point for transistor gates. Instead of directly connecting high-current transistor gates to the input node (which would increase input capacitance), the patent uses the output node as an intermediate connection, allowing these transistors to contribute to current driving capability without proportionally increasing input capacitance.
3Speed
If the settling time is reduced to enhance operation speed, then the operational speed is improved, but the voltage level stability deteriorates
Solution Approach 1:
The patent employs periodic switching of transistor gate connections based on operational phases. During signal acquisition phases, gates are connected to minimize input capacitance for fast settling. During signal hold phases, connections are adjusted to stabilize voltage levels. This periodic reconfiguration allows the system to achieve both fast settling and voltage stability at different times in the operational cycle.
Solution Approach 2:
The patent performs preliminary connection of transistor gates to the output node before the input signal changes, reducing the effective input capacitance in advance. This preliminary action prepares the circuit for fast settling by minimizing capacitance before the critical signal transition occurs, thereby achieving both speed and stability.
Data Source
AI summary
An operational amplifier includes a first transistor, a second transistor, a third transistor, a first constant current source, an output state, a first switch, and a second switch. The first transistor has a first gate configured to receive an output voltage from an output node. The second transistor has a second gate. The third transistor has a third gate configured to receive an input voltage. The first constant current source is coupled to sources of the first transistor, the second transistor, and the third transistor. The output stage is configured to drive the output voltage on the output node based on a first current through the first transistor, a second current through the second transistor, and a third current through the third transistor. The first switch is coupled between the second gate of the second transistor and the third gate of the third transistor; and the second switch is coupled between the output node and the second gate of the second transistor.