Switched High-Impedance Load Circuit Using Subthreshold Biasing
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Solution Overview
Problem
Existing electronic circuits face challenges in creating high-impedance loads for sensor applications while minimizing silicon surface area, as traditional solutions like low-doped sheet resistors and time-continuous current mirrors are process and temperature dependent, and costly, and require large areas, degrading small signals and increasing costs.
Innovation Solution
An electronic circuit with a capacitive element and non-linear elements like diodes or transistors, controlled by switching elements and timing logic, operates in charging, discharge, and transfer stages to establish and maintain a high-impedance load, using the subthreshold characteristics of MOSFETs or BJTs to achieve high impedance without large resistances, thus reducing silicon usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-doped sheet resistors are used to create high-impedance loads, then the impedance level is achieved, but the silicon area required becomes excessively large and parasitic capacitances increase
Solution Approach 1:
The patent changes the operating parameters of MOSFET transistors by biasing them in the subthreshold region, where the drain current exhibits exponential dependence on gate-source voltage. This parameter change enables the transistors to function as high-impedance elements without requiring large physical dimensions, thus achieving high impedance while minimizing silicon area.
Solution Approach 2:
The patent replaces passive resistive elements (low-doped sheet resistors) with active transistor-based circuitry that utilizes electrical field effects. This substitution eliminates the need for large physical resistance implementations and instead uses controlled current flow through transistors operated in specific regions to achieve the desired high-impedance characteristics.
2Reliability
If large-area resistors are used to achieve high impedance, then the impedance requirement is met, but parasitic capacitances increase and degrade small sensor signals
Solution Approach 1:
The patent changes the operational state of transistors to subthreshold biasing, fundamentally altering their electrical characteristics. In this regime, transistors exhibit very high output impedance and minimal capacitance effects, thereby achieving high impedance without the parasitic capacitance penalties associated with large physical resistors.
Solution Approach 2:
The patent substitutes physical resistor structures with transistor-based active impedance generation. This replacement eliminates the direct proportionality between resistance value and physical area, and consequently eliminates the associated parasitic capacitances that plague large-area resistor implementations.
3Ease of operation
If time-continuous current mirrors are used for high-impedance loads, then bias control is achieved, but the solution is unsuitable for pico-Ampere currents required for very high impedances
Solution Approach 1:
The patent changes the biasing regime from standard saturation operation to subthreshold operation, enabling the circuit to handle pico-Ampere current levels. This parameter change allows the current mirrors to operate accurately at extremely low current levels where conventional biasing schemes fail, while maintaining controllability through gate voltage manipulation.
4Area of stationary object
If subthreshold MOSFET characteristics are used to achieve high impedance, then silicon area is minimized, but accurate and repeatable biasing becomes complex
Solution Approach 1:
The patent segments the biasing function into distinct operational stages (charging, discharge, hold) controlled by timing logic. This segmentation breaks down the complex continuous biasing requirement into manageable discrete steps, making the subthreshold operation more controllable and repeatable while maintaining area efficiency.
Solution Approach 2:
The patent employs periodic switching sequences to establish and maintain the subthreshold bias conditions. By using periodic charge-discharge cycles of capacitive elements controlled by timing logic, the circuit achieves stable and repeatable bias points despite the inherent complexity of subthreshold operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit effectively presents a high-impedance load that is robust, cost-effective, and minimizes signal degradation, maintaining a well-controlled bias point and temperature stability, suitable for sensor applications like PIR sensors, while being implementable in standard manufacturing processes.
Implementation Method 1
a capacitive element (C) provided between a first node (Node A) and the reference point
Implementation Method 2
a first element (D1), being either a diode or a diode connected transistor, having a non-linear voltage-to-current relationship
Implementation Method 3
A more suitable solution may be to use subthreshold characteristics of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices, or to utilise the exponential current-voltage relationship of a diode or BJT (Bipolar Junction Transistor)
Data Source
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AI summary
An electronic circuit configured to present a high-impedance load between a load point (VL) and a reference point includes a capacitive element (C) provided between a first node (Node A) and the reference point, a first element (D1) connected in parallel with the capacitive element (C), a first switching element (S1) provided in series between the first node (A) and a voltage source point, a second switching element (S2) provided between the first node (A) and a second node (Node B), a second element (D2) connected between the second switching element (S2), the load point, and the reference point, and timing control logic configured to implement three stages. In a charging stage, the first switching element (S1) is closed and the second switching element (S2) to charge a nodal voltage vD(t) at the first node (A). In discharge stage, the first switching element (Si) is open and the second switching element (S2) is open to enable discharging of the capacitive element (C) through the first element (D1). In a transfer stage, the second switching element (S2) is closed to connect the first node (A) and the second node (B), after which the second switching element (S2) is opened and the second element (D2) is biased to present the high-impedance load.