Switched Memory Architecture Reduces Bus Contention
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Solution Overview
Problem
Current multi-channel memory controllers face limitations in data transfer efficiency due to memory bus congestion and contention, where commands and data can only be transferred through a single channel controller, leading to increased I/O latency and queue blocking.
Innovation Solution
A memory system utilizing a switched architecture with interconnected switching devices and multi-channel serial interfaces allows for data transfer between a memory controller and memory devices through any available channel, employing a time division multiplex (TDM) method to allocate dedicated timeslots and avoid congestion, enabling efficient data routing and access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single channel controller interfaces with a single set of memory dies, then the device complexity is reduced and ease of operation is improved, but memory bus congestion and contention occur leading to increased I/O latency and reduced productivity
Solution Approach 1:
The system segments the memory interface into multiple independent channel controllers, each capable of handling data transfers to/from different sets of memory dies simultaneously. This segmentation allows parallel data paths, eliminating the bottleneck of a single channel controller and reducing memory bus congestion while maintaining manageable device complexity through modular architecture
Solution Approach 2:
The patent introduces an intermediary switching fabric that connects multiple channel controllers to multiple memory die sets. This intermediary layer enables dynamic routing of data transfers, allowing any channel controller to access any memory die set when needed, thereby eliminating contention and improving overall system productivity without significantly increasing operational complexity
2Productivity
If multiple channel controllers share a common memory bus, then data transfer capacity is increased, but memory bus congestion and contention increase leading to queue blocking and increased I/O latency
Solution Approach 1:
The system implements dynamic resource allocation through the switching fabric, which can dynamically assign memory bus access to different channel controllers based on real-time demand. This dynamic approach allows the system to maintain high data transfer capacity while minimizing I/O latency by efficiently managing bus access and avoiding queue blocking through adaptive routing
Solution Approach 2:
The patent adds a temporal dimension to data transfer by implementing time-division multiplexing and asynchronous transfer modes. This allows multiple channel controllers to share the memory bus in different time slots without conflict, increasing overall data transfer capacity while maintaining low I/O latency for each individual transfer operation
Data Source
AI summary
A memory system for storing and retrieving data may include a controller, a first switch, a second switch connected to the first switch via an interconnecting bus, and a plurality of memory devices. The controller may have a first serial interface. The first switch may have one or more serial interfaces and one or more memory ports. The first serial interface of the controller may be communicatively connected to a first serial interface of the one or more serial interfaces of the first switch via a first serial bus. Each of the one or more memory ports of the first switch may be communicatively connected to a subset of the plurality of memory devices via a memory bus. The first switch may transfer data between the controller and the subsets of the plurality of memory devices via the one or more memory ports.