Switched Reference Voltages for Memory Read Sensing Accuracy

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Solution Overview

Problem

Memory devices face challenges in improving sensing accuracy due to voltage threshold mismatches between transistor pairs, leading to increased bit error rates and reduced reliability in read operations.

Innovation Solution

Implementing techniques that include offset cancellation and coupled amplification circuits to compensate for threshold mismatches, where a precharge voltage is applied to both memory and reference transistors, and a capacitive circuit is used to tune the reference voltage response to match the memory node, thereby reducing variability and enhancing sensing accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional read operations are used without offset cancellation, then device complexity is lower, but measurement precision deteriorates due to voltage threshold mismatches between transistor pairs

Engineering Contradiction:
Improvesensing accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing offset cancellation before the actual read operation. A precharge voltage is applied to both memory and reference transistors to pre-compensate for threshold voltage mismatches. This preliminary compensation ensures that when the actual read operation occurs, the sensing accuracy is improved without requiring complex real-time adjustment circuits.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary capacitive circuit that couples the memory node to tune the reference voltage response. This capacitive circuit acts as a mediator that matches the reference voltage characteristics to the memory node, thereby compensating for transistor threshold mismatches and improving sensing accuracy without directly modifying the transistor pair structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If offset cancellation techniques are implemented, then measurement precision improves, but device complexity increases due to additional circuits

Engineering Contradiction:
Improvesensing accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent employs parameter changes by dynamically adjusting the reference voltage level through a capacitive circuit. The reference voltage is tuned to match the memory node characteristics by changing its electrical parameters (capacitive coupling), which compensates for transistor threshold variations and improves sensing accuracy without adding complex structural elements.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If reference voltage tuning is applied, then manufacturing precision improves, but device complexity increases

Engineering Contradiction:
Improveconsistency of memory statesVSAvoidcircuit complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The capacitive circuit serves multiple functions: it tunes the reference voltage, compensates for threshold mismatches, and ensures consistent offset between memory states. This multi-functional approach improves manufacturing precision without requiring separate circuits for each function, thereby limiting the increase in overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11869587B2Techniques for read operations using switched reference voltages
Publication Date: 2024.01.09 MICRON TECHNOLOGY INC
  • US11869587B2 patent drawing
  • US11869587B2 patent drawing
  • US11869587B2 patent drawing

AI summary

Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.