Switched-Resistor DAC Architecture for Faster Low-Glitch Conversion
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Solution Overview
Problem
Current digital-to-analog converters (DACs) face limitations in terms of power consumption, speed, glitch magnitude, and area requirements, particularly in achieving efficient conversion of digital binary values to proportional analog outputs, especially when dealing with large numbers of bits.
Innovation Solution
A digital-to-analog converter system comprising multiple stages, including a most significant bits (MSB) stage, intermediate significant bits (ISB) stage, and least significant bits (LSB) stage, utilizing switched resistor networks and Gray code conversion to optimize resistance values and reduce switching-induced power consumption, with additional offset cancellation circuits to improve resolution and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional single-stage DAC architecture is used, then the circuit structure is simple, but the conversion speed is limited and glitch magnitude increases
Solution Approach 1:
The DAC is divided into multiple stages (first stage, second stage, third stage) that process different groups of digital input bits separately. Each stage contains switched resistor networks that convert its portion of digital bits to analog output. The stage outputs are then combined to produce the final analog output. This segmentation enables parallel processing of digital bits, significantly improving conversion speed while managing circuit complexity through modular design.
2Measurement precision
If high resolution DAC is implemented, then conversion accuracy improves, but power consumption increases
Solution Approach 1:
The patent employs switched resistor networks where resistors are dynamically connected or disconnected based on the digital input bits. Switches control the inclusion of specific resistors in the conversion circuit only when needed for the current digital value being converted. This dynamic configuration allows high-resolution conversion to be achieved with reduced average power consumption compared to always-active resistor networks, as resistors are only actively switched when their corresponding bits require conversion.
3Manufacturing precision
If conventional resistor networks are used, then the circuit area is reduced, but resistance values become excessively large
Solution Approach 1:
The overall resistance conversion function is segmented across multiple stages, with each stage handling a portion of the digital bits. This allows the use of smaller, more manageable resistance values in each stage rather than requiring extremely large resistance values in a single stage. The segmented approach distributes the resistance conversion task, enabling practical resistance values that can be implemented with standard semiconductor fabrication processes.
4Measurement precision
If multi-stage architecture is implemented, then conversion speed and resolution improve, but device complexity increases
Solution Approach 1:
Each stage in the multi-stage architecture is designed with a universal switched resistor network structure that can handle its assigned digital bits through the same fundamental conversion mechanism. The stages use similar circuit topologies and switching schemes, allowing the same design template to be replicated across multiple stages. This universality simplifies the overall design process and reduces the effective complexity increase, as each additional stage follows a predictable pattern rather than requiring entirely new circuit designs.
Data Source
AI summary
A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.