Switched-Resistor DAC Architecture for Precision and Low Glitch
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Solution Overview
Problem
Current digital-to-analog converters (DACs) face limitations in terms of power consumption, speed, glitch magnitude, and area requirements, particularly in achieving precise analog output voltage representations from digital inputs, especially when dealing with large binary values.
Innovation Solution
A digital-to-analog converter system comprising multiple stages, including a most significant bits (MSB) stage, intermediate significant bits (ISB) stage, and least significant bits (LSB) stage, utilizing switched resistor networks and Gray code conversion to efficiently generate analog outputs, with each stage optimizing resistor values and switch configurations to minimize resistance and maximize precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional single-stage DAC architecture is used, then device complexity is reduced, but manufacturing precision and measurement precision deteriorate due to inability to achieve precise analog output voltage representations
Solution Approach 1:
The DAC is divided into multiple stages (first stage, second stage, third stage) that process different groups of digital input bits separately. Each stage contains switched resistor networks that convert its portion of the digital input to an analog output. The stage outputs are then combined to produce the final analog output voltage. This segmentation allows each stage to be optimized for precision while managing overall device complexity.
2Area of stationary object
If larger resistance values are used in the resistor networks, then device area is reduced, but power consumption increases and switching-induced glitches become more severe
Solution Approach 1:
The patent employs switched resistor networks where the resistance values are dynamically changed based on the digital input bits. By using switches to selectively connect different resistance values, the system can achieve precise analog output without requiring permanently large resistance values. This dynamic parameter change allows optimization of both area and power consumption characteristics.
3Productivity
If switching speed is increased to improve conversion speed, then productivity is improved, but switching-induced power consumption and glitch magnitude increase
Solution Approach 1:
The conversion process is segmented across multiple stages, each handling a subset of the digital input bits. This allows the switching operations in each stage to be optimized independently, reducing the overall switching activity required compared to a single-stage implementation. The segmented approach enables faster conversion while minimizing switching-induced power consumption and glitches.
4Device complexity
If more digital input bits are processed in a single stage, then device complexity is reduced, but manufacturing precision deteriorates due to difficulty in achieving precise voltage representations
Solution Approach 1:
The digital input bits are divided into multiple groups, with each group processed by a separate stage. This segmentation enables each stage to be designed with optimized precision characteristics for its specific bit group, while the overall device complexity is managed through the modular multi-stage architecture. The precision benefits of segmentation outweigh the added complexity of multiple stages.
Data Source
AI summary
A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.