Switched-Resistor PLL Loop Filter for Low-Area Low-Noise Locking
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Solution Overview
Problem
Existing phase-locked loop (PLL) circuits face challenges in achieving low silicon area and low power consumption, particularly due to large capacitor requirements in analog PLLs and high 1/f noise, while digital PLLs struggle with power efficiency, especially in older CMOS processes.
Innovation Solution
The implementation of a switched resistor network in the loop filter of PLL circuits, which adjusts effective resistance based on pulsing properties of a control signal, reduces noise and power consumption by leveraging switched resistor networks, high gain phase detectors, and efficient frequency detection methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large capacitor is used in the loop filter of an analog PLL, then the loop filter can achieve proper filtering performance, but the silicon area increases significantly
Solution Approach 1:
The patent changes the resistance parameter dynamically by switching between different resistor values based on the lock status of the PLL. During frequency acquisition, a first resistor value is used, and during locked operation, a second resistor value is used. This dynamic parameter change allows the loop filter to achieve proper filtering performance with smaller capacitor values, thereby reducing silicon area while maintaining reliability
Solution Approach 2:
The patent introduces dynamic switching of resistor values in the loop filter based on the PLL's operational state. The circuit transitions from a static resistor configuration to a dynamic one where resistance values are adjusted according to whether the PLL is acquiring frequency or maintaining lock. This dynamic adaptation enables the system to achieve the desired loop filter performance with reduced capacitor size and silicon area
2Area of stationary object
If switching components are used in the loop filter to reduce area, then silicon area decreases, but noise performance may deteriorate
Solution Approach 1:
The patent employs periodic switching of resistor values synchronized with the PLL's operational phases. The switching occurs periodically between frequency acquisition mode and locked operation mode, with each phase using appropriately optimized resistor values. This periodic action allows the circuit to maintain low noise during locked operation while achieving proper filtering with reduced area through the switching mechanism
Solution Approach 2:
The patent uses dynamic switching of resistor values to optimize the noise performance of the loop filter. By transitioning between different resistance configurations based on lock status, the circuit minimizes noise generation from switching components while maintaining the area benefits. The dynamic adjustment ensures that noise-critical phases operate with optimized parameters
3Area of stationary object
If the loop filter resistance is increased to reduce capacitor size, then capacitor area decreases, but the time constant increases affecting response speed
Solution Approach 1:
The patent dynamically adjusts the resistance value in the loop filter based on the PLL's operational state. During frequency acquisition, a first resistor value provides a time constant optimized for fast response and rapid frequency hunting. During locked operation, a second resistor value provides a time constant optimized for low noise and stable filtering. This dynamic switching resolves the contradiction by providing different resistance values for different operational requirements, enabling reduced capacitor area without sacrificing response speed when needed
Solution Approach 2:
The patent implements periodic switching between different resistance values that correspond to different operational phases. During the frequency acquisition phase, the circuit uses a resistance value that enables fast response. During the locked phase, it switches to a resistance value that optimizes filtering performance. This periodic action allows the system to achieve reduced capacitor area while maintaining appropriate response characteristics for each operational mode
Data Source
AI summary
Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.