Switched-Resistor PLL Loop Filter for Low-Noise, Small-Area Locking
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Solution Overview
Problem
Existing phase-locked loop (PLL) circuits face challenges in achieving low silicon area and low power consumption, with analog PLLs requiring large capacitors and digital PLLs struggling with high power consumption due to continuous signal switching, especially in older CMOS processes.
Innovation Solution
The implementation of a switched resistor network in the PLL circuitry, which includes a switched resistor loop filter and phase detector, reduces the impact of 1/f noise and achieves high gain through pulsing properties of a control signal, allowing for a more efficient and compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a charge pump PLL with large capacitor is used in loop filter, then low 1/f noise performance is achieved, but silicon area increases significantly
Solution Approach 1:
The patent applies periodic action by using a switched resistor network that periodically switches between different resistance states based on the phase error signal. This periodic switching allows the loop filter to achieve high gain and low 1/f noise without requiring large capacitor values, as the time-varying resistance provides the necessary filtering characteristics dynamically rather than statically
Solution Approach 2:
The patent changes the resistance parameter dynamically through the switched resistor network, which modifies its effective resistance based on the phase error signal. This parameter change allows the loop filter to achieve different filtering characteristics at different operating conditions, providing low 1/f noise performance without the need for large fixed capacitors
2Adaptability or versatility
If digital PLL with continuous signal switching is used, then integration compatibility is improved, but power consumption increases
Solution Approach 1:
The patent uses periodic action by implementing a switched resistor network that only switches based on phase error detection rather than continuous switching. This reduces power consumption by eliminating unnecessary continuous signal switching while maintaining digital PLL integration compatibility, as the switching occurs only when phase correction is needed
Solution Approach 2:
The patent extracts the continuous switching operation from the digital PLL structure and replaces it with event-driven switching based on phase error detection. This removes the source of excessive power consumption while preserving the digital implementation advantages, by only activating switching when actually needed for phase correction
3Power
If switched resistor network with pulsing control is used, then gain is increased and area is reduced, but control complexity increases
Solution Approach 1:
The patent applies universality by making the phase detector serve multiple functions: it detects phase error and simultaneously generates the control signal for the switched resistor network. This multi-functionality reduces control complexity by eliminating the need for separate control logic, as the phase detector inherently provides both detection and control signal generation
Solution Approach 2:
The switched resistor network is self-controlled by the phase error signal it receives, automatically adjusting its resistance state based on the detected phase error without requiring external control logic. This self-service mechanism reduces control complexity by making the system self-regulating based on its own operational state
Data Source
AI summary
Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.