Switched-Element SAR ADC for Low-Power Charge Transfer MACs
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Solution Overview
Problem
Existing multiplier-accumulator architectures for machine learning applications face challenges in scalability and power consumption due to synchronous operation and increased gate complexity, particularly in performing multiply-accumulate operations, which require large numbers of adders and result in high power dissipation.
Innovation Solution
A scalable asynchronous multiplier-accumulator architecture utilizing a common charge transfer bus for multiplier-accumulator, bias, and analog-to-digital converter unit elements, with NAND-groups and charge transfer capacitors to minimize displacement currents and power consumption by enabling asynchronous operation and shared binary weighted charge transfer lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If synchronous clocked stages are used for multiplier operation, then operation timing is controlled, but power dissipation increases
Solution Approach 1:
The patent replaces continuous clocked operation with periodic charge transfer events. The multiplier operates through discrete charge transfer phases controlled by switch timing rather than continuous clock signals, reducing power dissipation while maintaining operational control through periodic activation of the charge transfer mechanism
Solution Approach 2:
The patent substitutes the mechanical clocked switching system with an electrical charge transfer system. Instead of using clock signals to control sequential operations, the system uses voltage-level controlled switches that transfer charge packets, eliminating the need for continuous clocking and associated power consumption
2Productivity
If large numbers of adders are used for multiply-accumulate operations, then computation capability is improved, but gate complexity increases
Solution Approach 1:
The patent combines multiplication and accumulation functions into a single charge transfer operation. Multiple partial products are accumulated by sequentially transferring charge to a shared summing node, eliminating the need for separate adder circuits and reducing gate complexity while maintaining multiply-accumulate functionality
Solution Approach 2:
The charge transfer bus and summing node serve multiple functions simultaneously: they act as multiplication output channels, accumulation registers, and summing circuits. This multi-functionality replaces the need for dedicated adders and separate storage elements, reducing overall device complexity
3Measurement precision
If n×n multiplier size is increased, then computation precision is improved, but gate complexity increases as n2
Solution Approach 1:
The patent segments the multiplication process into bitwise operations using NAND gates, where each bit pair produces a partial product. The partial products are then accumulated through sequential charge transfer rather than simultaneous addition, allowing high-precision multiplication to be achieved through modular, scalable stages rather than a monolithic complex circuit
Solution Approach 2:
The patent transitions from spatial complexity (multiple parallel adders in the traditional approach) to temporal complexity (sequential charge transfer operations). By moving the accumulation process into the time domain through sequential charge transfer, the system achieves high precision multiplication with reduced spatial gate complexity
Data Source
AI summary
An Analog to Digital Converter (ADC) for a multiplier accumulator generates a digital output associated with a charge transfer bus made of weighted charge transfer lines with capacitance associated with each charge transfer line, the charge transfer bus connected to groups of ADC unit elements (UE) which add or remove charge from each line of the charge transfer line, each group of ADC unit elements having a sign bit input and a step size input and controlled by an ADC controller which switches the groups of ADC UE in a successive approximation according to a comparison of a summed charge from the weighted charge transfer lines until the ADC UE charge equals the charge transfer line capacitance, each comparison generating a bit value of the digital output.