Switched Source Lines for Low Voltage Memory Read Margins
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Solution Overview
Problem
Conventional memory systems face challenges in maintaining read margins at low voltage operations due to leakage currents from unselected bitcells, leading to indistinguishable logic '0' and '1' values, which reduces memory density and read robustness.
Innovation Solution
The implementation of switched source lines (SSLs) that drive the source line as an inverse of the wordline, reducing leakage current from unselected rows and improving read margins by ensuring bitlines are pulled down only by the on-current of the selected bitcell, allowing for higher density and low minimum voltage operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If low voltage operation is used to reduce power consumption, then energy efficiency is improved, but read margins collapse due to leakage current from unselected bitcells
Solution Approach 1:
The patent segments the source line control by introducing separate source line select transistors (SSL0, SSL1) for each row, allowing independent control of leakage paths for unselected rows. This segmentation enables the selected row to have its source line connected to VDD while unselected rows have their source lines disconnected or connected to ground, thereby isolating leakage currents from unselected bitcells and maintaining read margins at low operating voltages.
Solution Approach 2:
The patent introduces source line select transistors as intermediary components between the source line and the bitcell source terminals. These intermediary transistors act as controllable switches that can isolate unselected rows from the source line, preventing their leakage currents from affecting the bitline voltage during read operations, thus enabling low voltage operation with maintained read margins.
2Device complexity
If conventional memory architecture is used, then simplicity is maintained, but density is limited due to the need for short columns to maintain read margins
Solution Approach 1:
The patent segments the source line control into row-specific select transistors, enabling long columns with many unselected rows to be used without compromising read margins. This segmentation allows each row to be independently controlled, preventing leakage accumulation from multiple unselected rows, thereby enabling high-density memory arrays with extended column lengths while maintaining architectural simplicity.
Solution Approach 2:
The patent changes the control parameter of the source line from a static connection to a dynamically controlled connection via source line select transistors. This parameter change enables the source line voltage to be selectively applied or disconnected for each row, allowing long columns to be used in high-density configurations while maintaining read margins through active leakage suppression.
3Device complexity
If unselected rows are not isolated, then device complexity is reduced, but leakage current from unselected rows degrades read margin
Solution Approach 1:
The patent extracts and isolates the leakage current paths from unselected rows by introducing source line select transistors that can disconnect these rows from the source line. By taking out the leakage paths from the active read path, the harmful leakage currents are prevented from affecting the bitline voltage, enabling low voltage operation with maintained read margins without excessive complexity.
Solution Approach 2:
The source line select transistors serve as intermediary components that mediate between the source line and unselected rows. These intermediaries can be controlled to disconnect unselected rows from the source line, thereby blocking leakage current paths while maintaining a relatively simple overall device structure compared to more complex isolation schemes.
Data Source
AI summary
Various implementations described herein refer to an integrated circuit having a memory structure with an array of bitcells accessible via wordlines arranged in rows and bitlines arranged in columns. The integrated circuit may include source lines coupled to the bitcells. The integrated circuit may include source line drivers coupled between the wordlines and the source lines, and the source line drivers may allow the source lines to be used as switched source lines.