Switched Differential Summation Circuit for Higher Common-Mode Rejection
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Solution Overview
Problem
Common-mode noise degrades the common-mode rejection ratio (CMRR) in differential to single-ended summation circuits due to parasitic capacitances and electromagnetic interference, leading to increased differential crosstalk and signal integrity issues.
Innovation Solution
A differential to single-ended summation circuit design that includes switches and capacitors to isolate parasitic capacitors from the holding capacitor, utilizing a summing, transfer, and reset phase operation to minimize common-mode noise impact, thereby improving CMRR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of transducer elements and LNAs increase to improve signal detection capability, then the signal detection capability is improved, but parasitic capacitances between differential lines and common potential increase, degrading CMRR
Solution Approach 1:
The patent segments the differential signal path into isolated capacitive nodes using switches. Each differential line has its parasitic capacitance isolated into separate holding capacitors, preventing the cumulative effect of multiple parasitic capacitances from degrading CMRR, while still allowing differential signals to be summed at the output.
Solution Approach 2:
The patent introduces holding capacitors and switches as intermediary elements between the differential lines and the summation node. These intermediaries capture and isolate the parasitic capacitance effects, preventing them from directly affecting the differential signal summation and output, thereby maintaining high CMRR despite multiple transducer elements.
2Object-affected harmful factors
If common-mode noise is present on differential lines, then electromagnetic interference is received, but common-mode noise degrades CMRR and increases differential crosstalk
Solution Approach 1:
The patent extracts common-mode noise from the differential signal path by using switches to redirect common-mode voltage components to ground or isolated nodes during the summation process. This extraction prevents common-mode noise from being converted into differential crosstalk and appearing at the output, maintaining signal integrity despite EMI presence.
Solution Approach 2:
The patent converts the harmful effect of parasitic capacitances and common-mode noise into a beneficial isolation mechanism. By intentionally capturing parasitic capacitance in holding capacitors and using switch-based isolation, the circuit transforms what would be sources of degradation into controlled elements that protect the differential summation from common-mode interference.
3Device complexity
If a conventional differential to single-ended summation circuit is used, then circuit simplicity is maintained, but common-mode noise appears as offset at the output and degrades CMRR
Solution Approach 1:
The patent introduces dynamic switching elements that change their state based on the operating phase (summation, transfer, reset). The switches dynamically connect and disconnect holding capacitors and isolation elements, enabling the circuit to maintain low complexity in terms of component count while achieving high CMRR through time-dependent isolation of parasitic capacitances and common-mode noise.
Data Source
AI summary
A differential to single-ended summation circuit includes a first switch which includes a first terminal coupled to a first circuit input and includes a second terminal. The circuit includes a second switch which includes a first terminal coupled to a second circuit input and includes a second terminal. The circuit includes a holding capacitor which includes a first terminal coupled to the second terminal of the first switch and a second terminal coupled to the second terminal of the second switch. The circuit includes a third switch which includes a first terminal coupled to the second terminal of the first switch and a second terminal coupled to a circuit output. The circuit includes a fourth switch including a first terminal coupled to the second terminal of the second switch and a second terminal coupled to a common potential.