Switching Capacitor Circuit With Low On-Resistance and Parasitic Capacitance
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Solution Overview
Problem
Existing switching capacitor generation circuits face challenges in simultaneously reducing the on-resistance and parasitic capacitance of switch elements, which affects the operation properties of oscillators and filters, particularly in achieving optimal quality factor and frequency adjustment.
Innovation Solution
The proposed switching capacitor generation circuit employs a single switch element with strategically designed P-channel and N-channel MOS transistors, along with resistors, to minimize on-resistance and parasitic capacitance by adjusting gate widths and lengths, and using control signals to selectively activate capacitors, thereby improving the switch element's operation properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate width of the N-channel MOS transistor is increased to reduce on-resistance, then the quality factor is improved, but the parasitic capacitance increases
Solution Approach 1:
The switching function is divided between two separate transistors (first N-channel MOS transistor and second P-channel MOS transistor) operating in complementary fashion. Each transistor handles only one state (on or off), eliminating the need for a single transistor to simultaneously minimize both on-resistance and parasitic capacitance. This segmentation allows optimization of each transistor's dimensions for its specific function.
Solution Approach 2:
Instead of using a single N-channel MOS transistor and trying to optimize it for both low on-resistance and low parasitic capacitance, the invention uses a P-channel MOS transistor to perform the switching function in the opposite manner. The P-channel transistor's complementary characteristics allow it to achieve low parasitic capacitance while the N-channel transistor provides the low on-resistance path when conducting.
2Speed
If the gate length of the N-channel MOS transistor is decreased to reduce on-resistance, then the switching speed is improved, but the parasitic capacitance increases
Solution Approach 1:
The switching function is divided between two separate transistors (first N-channel MOS transistor and second P-channel MOS transistor) operating in complementary fashion. Each transistor handles only one state (on or off), eliminating the need for a single transistor to simultaneously minimize both on-resistance and parasitic capacitance. This segmentation allows optimization of each transistor's dimensions for its specific function.
3Device complexity
If a single N-channel MOS transistor is used for switching, then the circuit complexity is reduced, but it is impossible to simultaneously minimize on-resistance and parasitic capacitance
Solution Approach 1:
The invention merges the switching function into a single integrated unit consisting of complementary N-channel and P-channel MOS transistors with shared capacitive elements. This combined structure achieves superior operation properties (simultaneously low on-resistance and low parasitic capacitance) while maintaining relatively simple circuit complexity, as the two transistors work together as a unified switching mechanism rather than separate independent switches.
Data Source
AI summary
A switching capacitor generation circuit which reduces the on-resistance and parasitic capacitance of a switch element and improves the operation properties of the switch element. The switching capacitor generation circuit, which has first and second output terminals, includes a first capacitor coupled to the first output terminal, a second capacitor coupled to the second output terminal, and a single switch element coupled between the first and the second capacitors.