Switching Capacitor Slew Rate Control for Balanced Signal Edges
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Solution Overview
Problem
Existing slew rate control devices require additional complex control circuits to balance rising and falling slopes, degrading signal quality due to parasitic capacitance effects in voltage controlled oscillators and amplifiers.
Innovation Solution
A slew rate control device using a switching capacitor, where a first capacitor controls the rising slope during a high clock signal state and a second capacitor controls the falling slope during a low clock signal state, with optional sensing and control units to adjust capacitance and equalize slopes, eliminating the need for additional control circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an additional control circuit is used to balance rising and falling slew rates, then the slew rate balance is improved, but the circuit complexity increases
Solution Approach 1:
The patent merges the slew rate control function with the existing clock signal distribution network by using the same clock signal to control both the main circuit and the slew rate control capacitors. This integration eliminates the need for separate control circuits while achieving balanced rising and falling slew rates through the switching action of existing clock phases.
Solution Approach 2:
The circuit uses its own internal clock signal phases to automatically control the switching of slew rate control capacitors. The clock signal itself serves as the control mechanism, creating a self-regulating system that balances slew rates without external intervention or additional control logic.
2Device complexity
If parasitic capacitance is present in the circuit, then the circuit operation is simplified, but the signal quality degrades due to unbalanced slew rates
Solution Approach 1:
The patent converts the harmful effect of parasitic capacitance into a beneficial control mechanism. By intentionally adding switching capacitors that exploit the same parasitic effects, the circuit achieves balanced slew rates. The parasitic capacitance, rather than being merely tolerated, becomes part of the control mechanism that enables symmetric rising and falling edges.
3Ease of manufacture
If the rising slope and falling slope are not identical, then the circuit design is simpler, but the signal quality is degraded
Solution Approach 1:
The patent introduces asymmetric switching capacitor configurations to achieve symmetric slew rates. By placing capacitors of different values or in different positions in the rising and falling paths, the circuit compensates for inherent asymmetries in the voltage controlled oscillator, ultimately achieving balanced signal edges while maintaining relatively simple design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for balanced rising and falling slopes, improving signal quality and system performance by stabilizing circuit operations without additional control circuits, enhancing reliability and efficiency.
Implementation Method 1
a first capacitor that is connected to a target circuit operated in response to a clock signal, and controls a rising slope of a signal output from the target circuit when the clock signal is in a high state; a switch that is connected to the first capacitor in parallel, receives a reverse signal of the clock signal, as a control signal, and is turned on when the clock signal is in a low state; and a second capacitor that is connected to the switch in series, and controls a falling slope of the signal output from the target circuit when the clock signal is in the low state
Data Source
AI summary
Disclosed is a slew rate control device using a switching capacitor which includes a first capacitor that is connected to a target circuit operated in response to a clock signal, and controls a rising slope of a signal output from the target circuit when the clock signal is in a high state; a switch that is connected to the first capacitor in parallel, receives a reverse signal of the clock signal, as a control signal, and is turned on when the clock signal is in a low state; and a second capacitor that is connected to the switch in series, and controls a falling slope of the signal output from the target circuit when the clock signal is in the low state.