Vehicle Switching Cell Layout to Isolate Parasitic Inductance
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Solution Overview
Problem
The existing power factor correction circuits in electric or hybrid vehicles suffer from malfunctions due to parasitic inductance generated by the second electronic track in the printed circuit, which affects the switching performance and causes overheating.
Innovation Solution
The electronic circuit design includes a separate third wired link to connect the control capacitor between the third terminal and the fifth terminal, avoiding electrical coupling with the second wired link and minimizing parasitic inductance effects across the entire circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the second electronic track connects the midpoint to both the second terminal and the capacitor, then space is saved on the printed circuit, but parasitic inductance is generated that causes switching malfunctions and overheating
Solution Approach 1:
The patent segments the connection path by introducing a third electronic track that is separate from the second track. The second track connects the midpoint to the second terminal, while the third track connects the capacitor between the third terminal and the fifth terminal. This segmentation eliminates the parasitic inductance problem by preventing the capacitor from being electrically coupled to the inductive second track, while still achieving compact layout through optimized routing of the separate tracks.
2Device complexity
If the second track connects the midpoint to the capacitor, then the circuit layout is simplified, but parasitic inductance causes voltage generation that prevents correct control of the high-side transistor
Solution Approach 1:
The patent divides the connection paths into separate segments: the second track handles the midpoint to second terminal connection, while the third track handles the capacitor connection. This segmentation isolates the capacitor from the parasitic inductance of the second track, ensuring that voltage generated across the inductance does not interfere with capacitor charging/discharging operations or high-side transistor control, while maintaining relatively simple circuit layout.
3Area of stationary object
If the capacitor is connected through the second track, then space is optimized, but switching losses increase due to parasitic inductance effects
Solution Approach 1:
The patent segments the electrical connections so that the capacitor connects via a dedicated third track separate from the inductive second track. This eliminates parasitic inductance in the capacitor charging/discharging path, reducing energy losses during switching operations. The layout remains optimized through careful routing of the separate tracks to minimize overall circuit area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration isolates the parasitic inductances, ensuring they do not influence the low-side switch and control capacitor, thereby improving switching performance, reducing overheating, and simplifying circuit parameterization.
Implementation Method 1
Each boot circuit comprises in particular a capacitor C, commonly called a 'bootstrap' capacitor by those skilled in the art, which is connected to the midpoint PM. More precisely, when the low-side switch T2 is closed and the high-side switch T1 is open, the capacitor C charges. Conversely, when the low-side switch T2 is open and the high-side switch T1 is closed, the capacitor C discharges.
Implementation Method 2
However, with reference to FIG. 2, this second track P2 generates a parasitic inductance Lp that can cause malfunctions in the switching of the switches. Preferably, when the switching cell operates in boost mode, in which the output voltage provided by the switching cell is greater than the input voltage, a voltage is generated across the terminals of the parasitic inductance Lp when the high-side switch T1 opens or when the low-side switch T2 closes.
Data Source
AI summary
An electronic circuit, including: a switching cell including a first switch, referred to as a “high-side” switch, and a second switch, referred to as a “low-side” switch, that are connected to one another by an intermediate wired link; a control module for controlling the switching cell, including a first, a second and a third connection terminal; the intermediate wired link including a fourth connection terminal and a fifth connection terminal; a second wired link configured to connect the second connection terminal and the fourth connection terminal; a third wired link that is separate from the second wired link and configured to connect the control capacitor between the third terminal and the fifth terminal.