Switching Chip Binarized Neural Network Execution
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Solution Overview
Problem
Existing neural network execution technologies face challenges in achieving low processing latency and high-throughput while being economically viable, particularly for large neural networks.
Innovation Solution
The method involves configuring a switching chip to execute binarized neural networks by encoding input vectors in packet headers and utilizing match-action tables to perform XNOR, bit counting, and sign operations, leveraging the chip's pipeline stages to efficiently process binary inputs and weights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional neural network execution methods are used, then processing accuracy is maintained, but processing latency increases and throughput decreases
Solution Approach 1:
The patent applies parameter changes by transforming the neural network model from using real-valued weights and activations to using binary weights and activations. This fundamental parameter transformation enables the use of bitwise operations instead of traditional multiply-accumulate operations, dramatically improving processing speed and reducing latency while maintaining acceptable accuracy through techniques like weight quantization and activation approximation.
2Speed
If more powerful general purpose servers are used to reduce processing latency, then processing speed improves, but economic viability deteriorates
Solution Approach 1:
The patent employs cheap short-living objects by utilizing standard switching chip hardware that is already widely deployed in network infrastructure. Instead of requiring expensive specialized AI accelerators or GPUs, the invention repurposes existing switching chip resources (parsers, match-action tables, pipeline stages) to execute binarized neural networks, making high-speed inference economically viable on commodity hardware.
Solution Approach 2:
The patent applies universality by enabling switching chips to perform dual functions: their original network packet forwarding role and neural network inference execution. The same hardware components (parsers for encoding input vectors, match-action tables for XNOR operations, pipeline stages for bit counting) are used for both traditional switching operations and BNN computation, maximizing resource utilization and economic efficiency.
3Productivity
If binarized neural networks are executed on switching chips, then processing throughput increases, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the neural network computation into distinct pipeline stages that correspond to the switching chip's existing architectural stages. Each stage performs a specific function (input encoding in parser, XNOR operations in match-action tables, bit counting in subsequent stages, sign operation in final stage), allowing parallel processing and maintaining throughput while managing complexity through modular stage-based organization.
Data Source
AI summary
A method for executing a binarized neural network (BNN) using a switching chip includes describing an artificial neural network application in a binarized form to provide the BNN; configuring a parser of the switching chip to encode an input vector of the BNN in a packet header; configuring a plurality of match-action tables (MATs) of the switching chip to execute, on the input vector encoded in the packet header, one or more of the operations including XNOR, bit counting, and sign operations such that the plurality of MATs are configured to: implement a bitwise XNOR operation between the input vector and a weights matrix to produce a plurality of first stage vectors, implement an algorithm for counting a number of bits set to 1 in the plurality of first stage vectors to produce a plurality of second stage vectors, and implement a sign operation on the second stage vectors.