Switching Circuit Latchup Prevention via Potential Control

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Solution Overview

Problem

Conventional switching circuits face the risk of latchup due to forward bias generation when enhancement-type P-channel MOS transistors become on, leading to uncontrollable switching and increased area requirements for guard rings or power source circuits to mitigate this issue.

Innovation Solution

A switching circuit design that includes a potential control circuit connecting a second well with a node during the transition of transistors from off to on, ensuring the potential of the second node is lower than the first node, and subsequently connecting it with the second node after a predetermined period, thereby preventing forward bias and latchup.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If enhancement-type P-channel MOS transistors are used for switching, then switching functionality is achieved, but forward bias is generated causing latchup risk

Engineering Contradiction:
Improveswitching functionalityVSAvoidlatchup risk
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

A potential control circuit is introduced as an intermediary between the transistors and the second well. This circuit temporarily connects the second well to the first node during transistor transition, controlling the potential relationship to prevent forward bias. The intermediary circuit mediates the interaction between transistors and wells, eliminating latchup risk while preserving switching functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The potential control circuit performs preliminary action by establishing the correct potential relationship between wells before the transistors fully turn on. By temporarily connecting the second well to the first node during the transition period, the circuit ensures that the potential of the second node remains lower than the first node, preventing forward bias from occurring in the first place.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If guard rings or power source circuits are added to prevent latchup, then reliability improves, but device area increases

Engineering Contradiction:
Improvelatchup preventionVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The potential control circuit serves multiple functions: it prevents latchup by controlling well potentials, manages the transition state of transistors, and maintains proper potential relationships during switching. This multi-functional approach eliminates the need for separate guard rings or additional power source circuits, achieving latchup prevention without increasing device area.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The latchup prevention function is merged with the existing transistor switching circuitry through the potential control circuit. Rather than adding separate protective structures like guard rings, the control circuit integrates well potential management into the switching operation itself, combining multiple functions into a unified circuit architecture that does not increase area.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9159379B2Switching circuit and semiconductor memory device
Publication Date: 2015.10.13 SOCIONEXT INC
  • US9159379B2 patent drawing
  • US9159379B2 patent drawing
  • US9159379B2 patent drawing

AI summary

A switching circuit includes a first well and a second well formed in a semiconductor substrate; a first transistor being connected with a first node at one end, and the first transistor being formed in the first well; a second transistor being connected with another end of the first node at one end, and connected with a second node at another end, and the second transistor being formed in the second well; and a potential control circuit that connects the second well with the first node during a predetermined period including a period for the first transistor and the second transistor to transition from off to on in a state where potential of the second node is lower than potential of the first node, and connects the second well with the second node after the predetermined period.