High Frequency Switching Circuit Power Reduction
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Solution Overview
Problem
Existing high frequency switching circuits fail to reduce power consumption during both signal reception and transmission, particularly in communication systems like UMTS where the voltage down circuit needs to operate at all times.
Innovation Solution
A high frequency switching circuit that includes a pulse generation unit, a clock selection unit, a voltage down unit, and a switching unit, where a clock selecting pulse signal activates a reference clock signal for power-down operations and switches to a low-speed clock signal for reduced power consumption, generating a negative voltage to maintain switches in a turned-off state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the voltage up circuit is operated only at transmission time, then power consumption is reduced at reception time, but power consumption cannot be reduced at transmission time in systems requiring continuous voltage down circuit operation
Solution Approach 1:
The patent applies dynamics by making the clock signal frequency adjustable based on operational mode. The clock selection unit dynamically switches between a first clock signal (higher frequency) during transmission and a second clock signal (lower frequency) during reception, allowing the voltage down circuit to adapt its operating speed to match the actual operational requirements, thereby reducing power consumption while maintaining system functionality.
Solution Approach 2:
The patent changes the clock frequency parameter based on communication mode. By selecting different clock signals with different frequencies for the voltage down circuit during transmission versus reception, the system optimizes power consumption without compromising the necessary voltage control functionality. This parameter adjustment resolves the contradiction between power saving and system adaptability.
2Speed
If a clock signal with high frequency is supplied to the voltage down unit, then the switching speed is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the clock frequency supplied to the voltage down circuit based on the communication mode. During transmission when high switching speed is needed, a higher frequency clock is supplied. During reception when speed requirements are lower, a lower frequency clock is supplied, thereby reducing power consumption while maintaining adequate switching performance.
Solution Approach 2:
The patent implements periodic action by alternating between different clock frequencies according to the communication mode. The clock selection unit periodically switches between the first and second clock signals based on whether the system is in transmission or reception mode, optimizing the balance between switching speed and power consumption for each operational phase.
3Use of energy by moving object
If the clock signal frequency is reduced, then power consumption is reduced, but the switching performance deteriorates
Solution Approach 1:
The patent applies dynamics by adjusting the clock frequency according to the actual operational needs. During transmission mode, the higher frequency clock maintains switching performance. During reception mode, the lower frequency clock reduces power consumption since high-speed switching is not required. This dynamic adjustment resolves the contradiction between power consumption and switching performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces power consumption during both signal reception and transmission, even in systems where the voltage down circuit must operate continuously, as demonstrated by a 60% reduction in current consumption compared to traditional methods.
Implementation Method 1
a voltage down unit accumulating negative charges in a capacitor at a speed according to the frequency of the clock signal selected in the clock selection unit to generate predetermined negative voltage
Data Source
AI summary
There is provided a high frequency switching circuit reducing power consumption at the time of signal reception and signal transmission. The high frequency switching circuit includes a pulse generation unit generating a clock selecting pulse signal having a predetermined active period; a clock selection unit selecting a reference clock signal when the clock selecting pulse signal is in an active state and selecting a low-speed clock signal having a frequency lower than that of the reference clock signal when the clock selecting pulse signal is not in an active state; a voltage down unit accumulating negative charges in a capacitor to generate predetermined negative voltage; and a switching unit including at least one switch holding a turned-off state by being applied with the predetermined negative voltage.