Switching Circuit Stacked Metal Layer Routing
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Solution Overview
Problem
The increasing capacitance between wires in miniaturized switching circuits, due to closer wire formations, negatively impacts the on-state resistance and overall performance of switching circuits, particularly in MOSFETs, as it increases the product of on-state resistance and capacitance, affecting switching performance.
Innovation Solution
The design of a switching circuit with specific wiring arrangements and layer configurations, including interleaved source and drain lines, shared metal layers, and optimized via connections, reduces interlayer crosstalk and capacitance, while maintaining uniform current density and reducing on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If wire spacing is reduced to achieve device miniaturization, then device size is reduced, but capacitance between wires increases
Solution Approach 1:
The patent transitions from planar wire routing to three-dimensional stacked routing across multiple metal layers. Wires that would be adjacent in two dimensions are separated by vertical stacking, with alternating source and drain lines distributed across different metal layers (M1, M2, M3) to reduce capacitive coupling while maintaining miniaturization
Solution Approach 2:
The wire routing is segmented into multiple discrete metal layers with via connections. Source lines and drain lines are separated into different layers (e.g., source in M1, drain in M2) with intermediate via wiring, breaking the continuous capacitive coupling that would exist in planar routing
2Volume of moving object
If wire spacing is reduced to achieve device miniaturization, then device size is reduced, but on-state resistance increases
Solution Approach 1:
Multiple wire segments across different metal layers are merged into a unified three-dimensional conductive path. The source line continues across M1, M2, M3 layers via via connections, and the drain line similarly spans multiple layers, creating parallel conductive paths that reduce overall resistance while maintaining compact footprint
Solution Approach 2:
The conductive paths extend into the vertical dimension across multiple metal layers, increasing the effective cross-sectional area for current flow. This three-dimensional routing provides multiple parallel conduction channels that reduce on-state resistance despite reduced planar dimensions
3Productivity
If wires are formed closer together for miniaturization, then device density increases, but interlayer crosstalk increases
Solution Approach 1:
Ground lines are introduced as intermediary elements between signal-carrying source and drain lines. These ground lines act as shields that redirect electromagnetic fields, reducing crosstalk between adjacent source and drain lines in the stacked configuration
Solution Approach 2:
Different metal layers are assigned different functional roles based on their local position: source lines in M1, drain lines in M2, with ground lines strategically placed in M3. This local differentiation optimizes each layer's contribution to signal integrity while maintaining high density
Data Source
AI summary
A switching circuit comprises a first transistor and a second transistor formed in an active area of semiconductor substrate. The source and drain regions of the transistors are electrically connected to respective source wires and drain wires through a plurality of intermediate metal layers stacked above the transistor. Electrical connections between different layers are made with a plurality of vias. To improve switching performance, the intermediate wires are disposed such that intermediate wires electrically connected to the transistor source regions are not directly beneath the drain wires. Similarly, intermediate wires electrically connected to drain regions are arranged not to be directly underneath source wires.