Wire-Bond-Free Switching Circuit Layout for Faster Power Switching
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Solution Overview
Problem
Existing power electronic circuits face limitations in maximum achievable current density and switching speed due to bonding wires, which introduce parasitic inductances and restrict the performance of semiconductor components.
Innovation Solution
The electronic circuit design features multiple circuit carriers and semiconductor components connected directly through plated-through holes and conductive tracks without bonding wires, utilizing chip bonding for connections, which enhances current density and switching speed while improving thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bond wires are used to contact semiconductor components, then ease of manufacture is improved, but current density and switching speed are limited due to parasitic inductances
Solution Approach 1:
The patent extracts and eliminates the bond wire from the circuit configuration. Instead of using bond wires to connect semiconductor components to the circuit carrier, the invention directly contacts the semiconductor components' contact surfaces with conductor tracks on the circuit carrier, removing the source of parasitic inductance entirely
Solution Approach 2:
The patent merges the function of the bond wire connection with the circuit carrier's conductor track system. The semiconductor component is directly mounted on the circuit carrier such that its contact surfaces are electrically connected to conductor tracks, combining the mounting and electrical connection functions into a single integrated structure
2Ease of manufacture
If bond wires are used to contact semiconductor components, then ease of manufacture is improved, but maximum permissible current density is limited
Solution Approach 1:
The patent extracts and eliminates the bond wire from the circuit configuration. Instead of using bond wires to connect semiconductor components to the circuit carrier, the invention directly contacts the semiconductor components' contact surfaces with conductor tracks on the circuit carrier, removing the source of parasitic inductance entirely
Solution Approach 2:
The patent transitions from a point-to-point connection (bond wire) to a surface-to-surface connection (semiconductor contact surface directly on circuit carrier conductor track). This dimensional change from linear to planar contact area enables higher current density by distributing current flow over a larger effective area
3Device complexity
If bond wires are used to contact semiconductor components, then device complexity is reduced, but parasitic inductances arise that limit switching speed
Solution Approach 1:
The patent extracts and eliminates the bond wire from the circuit configuration. Instead of using bond wires to connect semiconductor components to the circuit carrier, the invention directly contacts the semiconductor components' contact surfaces with conductor tracks on the circuit carrier, removing the source of parasitic inductance entirely
Solution Approach 2:
The patent converts the potential complexity of direct mounting into a benefit by eliminating parasitic inductance. The direct contact configuration, while requiring precise alignment, eliminates the harmful parasitic inductance of bond wires, resulting in superior electrical performance that outweighs the manufacturing precision requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration eliminates parasitic inductances, allows for higher current-carrying capacity, and improves thermal dissipation, resulting in a more compact and efficient power electronic circuit with enhanced switching performance.
Implementation Method 1
The first connecting element establishes a material-bonded, and in particular electrical, connection between the top side of the second circuit carrier and the underside of the first circuit carrier
Implementation Method 2
The first circuit carrier has a first via that electrically connects the top surface of the first semiconductor device to a first conductor track of the first circuit carrier
Data Source
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AI summary
For the purpose of improved performance, an electronic circuit (7) having a first and a second circuit carrier (6, 8) and a first and a second semiconductor component (9, 10) is provided. The first semiconductor component (9) lies with its upper side on an underside of the first circuit carrier (6) and with its underside on an upper side of the second circuit carrier (8). The first circuit carrier (6) has a first via (11) which connects the first semiconductor component (9) to a first conducting path. The first circuit carrier (6) has a second via (13) which electrically connects a connection element (14) arranged between the circuit carriers to a further conducting path. An integral connection is formed between the circuit carriers using the first connection element (14). The second semiconductor component (10) lies against the underside of the first circuit carrier (6) and is electrically connected to the first or second conducting path. The circuit (7) comprises a third circuit carrier (17), wherein an underside of the second semiconductor component (10) lies against an upper side of the third circuit carrier (17). A lateral thermal expansion coefficient of the first circuit carrier (6) is greater than or equal to a lateral thermal expansion coefficient of the second circuit carrier (8) and is greater than or equal to a lateral thermal expansion coefficient of the third circuit carrier (17).