Switching Control Circuitry for Processor Core Latency
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Solution Overview
Problem
Current data processing systems, such as those employing big.LITTLE processors, face inefficiencies due to the coarse granularity of switching between high and low power processor cores, leading to suboptimal performance and power management as changes in workload requirements occur at a finer level than the systems can handle.
Innovation Solution
The implementation of switching control circuitry that accounts for latency when transitioning between different execution mechanisms by transferring architectural state data and controlling the switching operation based on latency indicating signals, allowing for speculative execution and early transfer of register state data to minimize latency and improve switching efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire processor state is transferred between processor cores during switching, then the switching operation is complete and reliable, but the switching latency becomes excessively long (hundreds to thousands of cycles)
Solution Approach 1:
The processor state transfer is segmented into multiple categories: fully transferred state elements, partially transferred state elements, and non-transferred state elements. This segmentation allows the switching operation to complete critical transfers quickly while deferring less critical transfers, thereby reducing overall switching latency while maintaining reliability.
Solution Approach 2:
The system performs preliminary actions by predicting future switching operations and pre-transferring state elements before the actual switch is needed. This eliminates or reduces the latency of the critical path by having state data ready in advance, while maintaining reliability through validation mechanisms.
2Reliability
If switching is performed with coarse granularity (transferring entire processor state), then switching reliability is ensured, but the system cannot adapt to fine-grained workload changes occurring at the cycle level
Solution Approach 1:
The processor state is segmented into multiple categories with different transfer priorities and granularities. Critical state elements are transferred fully and reliably, while less critical elements are transferred partially or deferred, enabling the system to adapt to fine-grained workload changes while maintaining stability for essential operations.
Solution Approach 2:
Different state elements are treated with different qualities of transfer: some are fully transferred with high reliability, others are partially transferred with lower reliability. This local differentiation allows the system to adapt to varying workload requirements at different granularities while ensuring critical functions maintain high stability.
3Use of energy by moving object
If the processor switches between high performance and low power cores, then power efficiency is improved during low workload periods, but the switching latency prevents timely response to changing performance requirements
Solution Approach 1:
The system performs preliminary state transfers and predictions to prepare for upcoming switching operations. By pre-transferring state elements before the actual switch is triggered, the system can respond more quickly to changing performance requirements while maintaining the power efficiency benefits of switching between high and low power cores.
Solution Approach 2:
The switching mechanism is made dynamic by allowing the granularity and completeness of state transfers to vary based on the urgency and nature of the workload change. This enables timely switching when performance requirements change rapidly while maintaining power efficiency during gradual or predictable transitions.
Data Source
AI summary
A data processing apparatus includes a first execution mechanism, such as an out-of-order processing circuitry, and a second execution mechanism 6 such as an in-order processing circuitry. Switching control circuitry controls switching between which of the first execution circuitry and the second execution circuitry is active at a given time. Latency indicating signals indicative of the latency associated with a candidate switching operation to be performed are supplied to the switching control circuitry and used to control the switching operation. The control of the switching operation may be to accelerate the switching operation, prevent the switching operation, perform early architectural state data transfer or other possibilities.