Switching Controller Read Latency Reduction via Pre-Read

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Solution Overview

Problem

Conventional information processing systems experience high latency due to the number of cycles required for a read command to reach a device, leading to performance degradation, especially when commands or data pass through multiple paths.

Innovation Solution

Incorporating a switching controller with a command detection circuit, a command processing circuit, a selector, and a pre-read request issuance circuit to detect and process read commands, generate pre-read requests, and reduce the number of cycles by processing read commands with a pre-read process, thereby reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If read commands pass through multiple paths in the conventional system, then data can be transferred between CPU, memory, and device, but latency increases significantly (6 cycles)

Engineering Contradiction:

Improveread latencyVSAvoidnumber of paths

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The switching controller performs preliminary actions by detecting read commands early and generating pre-read requests for data that will be needed soon. This allows data to be fetched from memory in advance before the actual read command reaches the device, reducing the overall latency of the read operation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The switching controller acts as an intermediary between the CPU, memory, and device. It intercepts read commands, processes them independently by generating pre-read requests, and manages the data flow between components. This intermediary role allows the system to optimize data transfer paths and reduce latency without requiring changes to the fundamental system architecture.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If the system uses a serialized interface to secure high bandwidth, then data transfer capacity increases, but latency in serial/parallel conversion units becomes very high

Engineering Contradiction:

ImprovebandwidthVSAvoidconversion latency

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The pre-read mechanism ensures continuous useful action by keeping the memory and device busy with data transfer operations. While the device is processing or waiting, the switching controller continuously issues pre-read requests, ensuring that data is ready when needed and minimizing idle time in the system.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS8898343B2Information processing apparatus and control method thereof

Publication Date: 2014.11.25 FUJITSU LTD

AI summary

An information processing apparatus includes a processing unit configured to issue a read command to a device, a memory configured to store data, and a switching controller configured to connect the processing unit, the memory, and the device. The switching controller includes a command detection circuit configured to detect the read command issued from the processing unit, a command processing circuit configured to process the read command and to output the processed read command, and a pre-read request issuance circuit configured to generate a read request for at least part of data within data specified by the read command and to transmit the read request to the memory. The switching controller receives the part of the data from the memory, and transmits the part of the data to the device.