Switching Frequency Synchronization Circuit Without PLL Complexity
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Solution Overview
Problem
Conventional switching frequency synchronization in power supply devices relies on complex phase-locked loop circuits, increasing design difficulty and cost.
Innovation Solution
A switching frequency synchronization circuit that uses voltage comparison and synchronization to align internal and external clock frequencies without a phase-locked loop, utilizing a first oscillator, voltage generating circuit, comparison unit, and switching control circuit to reset the internal clock signal based on peak value and time difference comparisons.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase-locked loop circuit is used to synchronize the internal clock signal with the external clock signal, then the frequency synchronization is achieved, but the circuit structure becomes complex and the design cost increases
Solution Approach 1:
The patent extracts the essential function of frequency synchronization from the complex phase-locked loop circuit, keeping only the core components (oscillator, comparison unit, and reset mechanism) while removing unnecessary complexity. This allows frequency synchronization to be achieved with a simplified circuit structure.
Solution Approach 2:
The patent uses a simplified approach by copying only the essential synchronization mechanism rather than implementing the full phase-locked loop circuit. The internal oscillator's charging voltage signal is compared with the external clock's charging voltage signal, and the reset timing is adjusted to achieve frequency synchronization without replicating the entire PLL structure.
2Reliability
If a phase-locked loop circuit is used to synchronize the internal clock signal with the external clock signal, then the frequency synchronization is achieved, but the system stability time increases
Solution Approach 1:
The patent performs preliminary frequency comparison between the internal and external clocks before synchronization. The comparison unit evaluates whether the external clock frequency meets the synchronization requirement in advance, and only then proceeds with the frequency adjustment, reducing the time needed for system stabilization.
Solution Approach 2:
The patent skips the lengthy stabilization process of traditional phase-locked loops by directly resetting the internal oscillator based on the comparison result. When the external clock frequency is within the acceptable range, the system rapidly adjusts to the synchronized frequency without going through multiple stabilization cycles.
3Reliability
If a phase-locked loop circuit is used to synchronize the internal clock signal with the external clock signal, then the frequency synchronization is achieved, but the design difficulty increases
Solution Approach 1:
The patent segments the frequency synchronization function into distinct modular components: an oscillator that generates the internal clock, a comparison unit that evaluates frequency compatibility, and a reset mechanism that adjusts the oscillator frequency. This modular segmentation simplifies the design process and makes each component easier to implement and manufacture.
Solution Approach 2:
The system performs self-service frequency synchronization by automatically comparing the external clock frequency with the internal oscillator frequency and adjusting itself without requiring complex external control circuits. The comparison unit and reset mechanism work together to autonomously achieve and maintain frequency synchronization.
Data Source
AI summary
The present application discloses a switching frequency synchronization circuit, a method therefor and a switching power supply. By comparing peak values of a second charging voltage signal which represents an internal clock signal and a first charging voltage signal which represents an external clock signal, it is determined whether the frequency of the external clock signal meets the requirement for frequency synchronization. In a case that the frequency meets the requirement, the second charging voltage signal is reset by the external clock signal to synchronize the frequency of the internal clock signal with the frequency of the external clock signal. The present disclosure does not need a complex phase-locked loop circuit, and adjust an internal clock frequency by simple voltage comparison and synchronization mode. The control circuit is simplified and the overall system cost is reduced.