Switching Mode Power Supply Asynchronous Limiter Circuit
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Solution Overview
Problem
Switching mode power supply devices with control circuits on integrated circuits face reliability issues due to overvoltages caused by parasitic inductances and resistances in connecting members, leading to transistor weakening.
Innovation Solution
Incorporating a limiter circuit between the drain and source of MOS power transistors to reduce current variations during switching, comprising series-mounted MOS transistors, resistances, and capacitors that are only active during switching to maintain drain-source voltage below a threshold, thereby reducing overvoltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If switching mode power supply uses connecting members with non-zero inductance to connect power transistors to external circuits, then electrical connection is established, but overvoltages occur at drain-source and gate-source voltages during switching
Solution Approach 1:
The patent introduces a limiter circuit as an intermediary component between the power transistors and the connecting members with parasitic inductance. This limiter circuit actively monitors and limits the voltage spikes generated during switching operations, preventing overvoltages from reaching the transistors while allowing the connecting members to maintain their electrical connection function.
Solution Approach 2:
The limiter circuit is designed to activate before overvoltages can cause damage to the transistors. By detecting the onset of voltage spikes during switching and immediately counteracting them through controlled current limiting, the circuit prevents the harmful overvoltages from developing to damaging levels, thus protecting the transistors proactively.
2Reliability
If parasitic inductances and resistances are present in connecting members, then electrical connection is maintained, but voltage instabilities occur during transistor switching
Solution Approach 1:
The limiter circuit serves as a mediator that isolates the unstable switching transitions from the rest of the circuit. It absorbs and dampens the voltage instabilities generated by parasitic inductances and resistances during switching, providing stable voltage conditions to the transistors while allowing the connecting members to maintain their electrical connection.
Solution Approach 2:
The limiter circuit dynamically changes its electrical parameters (resistance, current limiting thresholds) during switching events to counteract the effects of parasitic inductances and resistances. By adjusting these parameters in response to detected voltage instabilities, the circuit maintains stable operating conditions for the transistors throughout the switching cycle.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The limiter circuit effectively limits overvoltages between the drain and source of power transistors, maintaining the drain-source voltage below a predetermined value and enhancing the reliability of the transistors by reducing voltage instabilities during switching.
Implementation Method 1
a capacitor (C1) mounted between the gate of the MOS transistor P2 and the drain of the MOS power transistor P1
Implementation Method 2
A connecting member may be modelized as an inductance Lp mounted in series with a resistance Rp... The inductance value L is of the order of a few nanohenries (nH)
Data Source
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AI summary
The invention relates to a switching mode power supply device comprising at least one MOS power transistor (P1;N11) made on an integrated circuit (CI; CI') and operating in switching mode, the drain and the source of said at least one MOS power transistor being connected, via connecting members (CN1, CN3; CN11, CN12) having a non-null inductance, to one or several external circuits to said integrated circuit. According to the invention, the device further comprises a limiter circuit (R1, C1, P2, P3) able to limit the current variations in at least one of said connecting members during the switching of said MOS power transistor. This limiter circuit (R1, C1, P2, P3) enables to maintain the drain -source voltage of the MOS power transistor below a predetermined threshold value when it commutes.