Switching Network for Convolutional Neural Network Data Distribution
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Solution Overview
Problem
Existing hardware implementations of spiking convolutional neural networks face challenges with parallel data access due to routing and concurrency issues, particularly when using multistage interconnection networks (MINs) that are not compatible with analogue signals and lack flexibility in handling circular shifts.
Innovation Solution
A device with a switching network controlled by a control unit, capable of applying circular shifts to convolution kernel coefficients, dynamically configures switches in response to input events and kernel parameters, allowing parallel data access in a convolutional neural network processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multistage interconnection networks (MINs) are used for parallel data access, then routing capability is improved, but compatibility with analogue signals is lost and flexibility for circular shifts is reduced
Solution Approach 1:
The patent implements dynamic switching networks that can reconfigure their connection topology based on the required circular shift amount. Unlike static MINs, these switches can adapt their routing paths dynamically, allowing the same hardware to support variable circular shifts while maintaining parallel access capability. The switching network changes its internal configuration to route data through different paths corresponding to the desired shift amount.
Solution Approach 2:
The invention changes the operational parameters of the switching network to accommodate both parallel access and circular shift requirements. By modifying the routing parameters and switch configuration states based on the input event and kernel parameters, the system achieves flexibility without sacrificing speed. The switching network operates in different modes depending on the required operation.
2Quantity of substance
If separate digital memory is used to store convolution kernel coefficients, then storage capability is improved, but memory access complexity and routing overhead increase
Solution Approach 1:
The patent merges the memory storage function with the switching network by implementing distributed memory architecture where kernel coefficients are stored locally at or near the processing elements. This integration eliminates the need for complex centralized memory access and reduces routing overhead, as the coefficients are already positioned where they are needed for computation.
Solution Approach 2:
The system performs preliminary distribution of kernel coefficients to the appropriate processing elements before the convolution operation begins. This pre-positioning of data eliminates the need for complex real-time routing during computation, as the coefficients are already in place and can be accessed directly by the processing elements.
3Ease of operation
If conventional switching networks are used for data distribution, then routing capability is improved, but concurrency of access to data creates problems
Solution Approach 1:
The patent segments the data distribution network into multiple independent switching stages and pathways. By dividing the routing function across multiple segments, concurrent access requests can be handled in parallel without interference. Each segment operates independently, allowing simultaneous data flows to proceed without conflicts or race conditions.
Solution Approach 2:
The switching network acts as an intermediary layer between memory and processing elements, managing concurrent access requests through coordinated switching. The intermediary switches buffer and route multiple data streams simultaneously, resolving potential conflicts before data reaches the processing elements, thereby ensuring reliable concurrent access.
Data Source
AI summary
A device for distributing the convolution coefficients of the least one convolutional kernel of a convolutional neural network is provided, the coefficients being carried by an input bus, to a set of processing units in a processor based on a convolutional-neural-network architecture. The device comprises at least one switching network that is controlled by at least one control unit, the switching network comprising a set of switches that are arranged to apply circular shifts to at least one portion of the input bus. For each convolution kernel, each control unit is configured to dynamically control certain at least of the switches of the switching networks in response to an input event applied to the convolution kernel and at least one parameter representing the maximum size of the convolution kernels.


