Multiple Switching Point Circuit for Metastable Signal Sampling
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Solution Overview
Problem
Existing devices struggle to efficiently handle metastable signals, particularly in asynchronous clock domains, where timing constraints are difficult to impose, leading to indeterminate convergence periods and improper signal sampling.
Innovation Solution
A device with a multiple switching point circuit connected between two latches, which receives feedback signals and output signals to activate pull-up and pull-down transistors, ensuring a stable output only after both latches converge to a stable state, preventing the propagation of undefined signals and managing metastable states effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a synchronizer samples data from an asynchronous circuit, then data transfer between clock domains is enabled, but the data signal may be sampled during metastable range leading to indeterminate convergence period
Solution Approach 1:
The patent introduces a multiple switching point circuit as an intermediary between the first latch and the second latch. This circuit monitors the output of the first latch and only allows data to be transferred to the second latch when the first latch has converged to a stable state, thereby preventing metastable signals from propagating to the next clock domain while maintaining data transfer capability
Solution Approach 2:
The multiple switching point circuit uses feedback from the first latch output to control the switching points. By detecting whether the first latch has stabilized, the feedback mechanism dynamically adjusts when data can be sampled by the second latch, ensuring reliable operation without compromising data transfer versatility
2Measurement precision
If timing constraints are imposed on asynchronous circuits, then proper sampling can be achieved, but it is difficult to impose timing constraints on circuits that are not clocked
Solution Approach 1:
The first latch operates autonomously without external clocking, sampling data asynchronously when ready. The multiple switching point circuit then self-regulates the data flow to the second latch based on the first latch's convergence status, eliminating the need for complex external timing constraints while maintaining sampling accuracy
3Reliability
If complex circuits with finite and predictable metastable time are used, then metastability can be managed, but device complexity increases
Solution Approach 1:
The multiple switching point circuit serves as a relatively simple intermediary that monitors latch convergence and controls data flow. Rather than using complex metastability management circuits, this intermediary approach provides reliable metastability handling with minimal additional complexity by simply waiting for stable state detection
Data Source
AI summary
A method and device for managing metastable signals. The device includes: a first latch and a second latch, a multiple switching point circuit, connected between an output node of the first latch and an input node of the second latch, wherein the multiple switching point circuit includes at least one pull up transistor and at least one pull down transistor that are selectively activated in response to a feedback signal provided from the second latch and in response to a an output signal of the first latch such as to define at least a low switching point that is lower than a high switching point of the multiple-switching point circuit; wherein a switching point of an inverter within the first latch is between the high and low switching points.