Switching Power Source Duty Cycle Control via Delay Circuit
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Solution Overview
Problem
Conventional switching power source apparatuses face a duty restriction due to internal delays in the PWM comparator, which prevents a decrease in output voltage, especially at higher switching frequencies.
Innovation Solution
Incorporating a delay circuit that generates an on-signal by delaying the clock signal to match the internal delay of the PWM comparator, allowing the PWM comparator to accurately compare error and slope voltages, thus eliminating the duty restriction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the switching frequency is increased, then the productivity is improved, but the output voltage control deteriorates due to duty restriction caused by PWM comparator internal delay
Solution Approach 1:
The patent applies preliminary action by generating the on-signal with a predetermined delay before the clock signal edge that triggers the PWM comparator. This advance delay compensates for the internal processing time of the PWM comparator, ensuring that the comparator receives accurate timing signals even at high switching frequencies. The delay amount is set to match the internal delay of the PWM comparator, allowing the system to maintain proper duty cycle control without restriction.
2Power
If the switching frequency is increased, then the power density is improved, but the duty cycle accuracy deteriorates due to internal delay effects
Solution Approach 1:
The patent uses copying by creating a delayed copy of the clock signal to generate the on-signal. This copied signal with predetermined delay mirrors the timing characteristics needed to compensate for the PWM comparator's internal delay. By using this copied and delayed timing signal, the system maintains accurate duty cycle measurement and control even when operating at high switching frequencies that would otherwise cause duty restriction.
Data Source
AI summary
A switching power source apparatus includes: a switching output circuit that generates an output voltage from an input voltage; an error amplifier that generates an error voltage in accordance with a difference between a predetermined reference voltage and the output voltage or a feedback voltage corresponding to the output voltage; a clock signal generation circuit that generates a clock signal; a slope voltage generation circuit that receives the clock signal to generate a slope voltage; a delay circuit that delays the clock signal to generate an on-signal; a PWM comparator that compares the error voltage and the slope voltage with each other to generate an off-signal; a logic circuit that receives the on-signal and off-signal to generate a pulse width modulation signal; and a switch drive circuit that receives the pulse width modulation signal to generate a drive signal for the switching output circuit.