Switching Power Supply Controller Timing Adjustment

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Solution Overview

Problem

In switching power supplies with multiple DC-DC converters, adjacent channels' switching timings that are close can lead to increased input current and switching noise due to overlapping ON periods, especially when one converter's switching timing depends on factors other than the clock signal.

Innovation Solution

A controller with a difference detector and timing adjuster is used to detect the difference between switching timings of adjacent channels and adjust the clock signal timing for one channel to increase the difference between the switching timings, thereby reducing noise by ensuring non-overlapping rising timings of LX potentials.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If switching timings of adjacent channels are made close to each other, then productivity is improved through efficient power supply operation, but switching noise increases due to overlapping ON periods causing momentary input current increase

Engineering Contradiction:
Improvepower supply operation efficiencyVSAvoidswitching noise
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent implements dynamic timing adjustment where the timing adjuster continuously monitors switching timings of adjacent channels and dynamically shifts clock signal phases to maintain optimal separation. This dynamic control allows the system to adapt switching timings based on operational conditions, preventing noise while maintaining efficiency.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The timing detector provides feedback about the actual switching timing differences between channels to the timing adjuster. This feedback mechanism enables closed-loop control where the system continuously monitors and corrects timing deviations, ensuring that switching noise is prevented while maintaining efficient operation.

Inventive Principle:
Principle #23Feedback

2Object-generated harmful factors

If clock signal timings are shifted to prevent overlapping switching, then switching noise is reduced, but device complexity increases due to additional timing control circuitry

Engineering Contradiction:
Improveswitching noiseVSAvoidtiming control circuitry
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The timing detector and adjuster circuitry is designed to be universally applicable across multiple channel configurations. The same basic circuit architecture can handle any number of adjacent channels by detecting timing relationships between any pair of channels, reducing the need for channel-specific control logic and minimizing overall complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system uses the existing clock signals and switching waveforms from the power supply channels themselves to generate the timing detection and adjustment functions. The timing detector utilizes the natural switching transitions to generate detection signals, and the timing adjuster uses the detected timing information to automatically adjust clock phases, making the control circuitry self-sufficient and reducing external control requirements.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8928177B2Control circuit and electronic device
Publication Date: 2015.01.06 SPANSION LLC
  • US8928177B2 patent drawing
  • US8928177B2 patent drawing
  • US8928177B2 patent drawing

AI summary

A controller includes a difference detector that detects a difference between a switching timing of a first channel of a switching power supply including a plurality of channels, and a switching timing of a second channel of the switching power supply, the plurality of channels being coupled in common to an input power supply and performing switching operations in response to clock signals, and a timing adjuster that, based on a detection result of the difference detector, increases a difference between a timing of a clock signal supplied to the first channel and a timing of a clock signal supplied to the second channel when the difference between the switching timing of the first channel and the switching timing of the second channel is smaller than a first value.