Switching Regulator Clock Control for Sleep Mode Power Efficiency

The patent implements periodic clock cycles during sleep mode, where the oscillator generates clock signals at reduced frequency. The control circuit periodically updates the output voltage regulation during these clock cycles, ensuring the voltage remains within the normal operation range while achieving ultra-low current consumption between updates. This periodic action resolves the contradiction by balancing power savings with voltage stability maintenance.

The patent dynamically adjusts the clock signal characteristics based on operating conditions. During sleep mode, the oscillator generates clock signals at a first frequency, and the control circuit dynamically determines whether to update the output voltage regulation based on whether the voltage remains within the normal operation range. This dynamic adaptation allows the system to minimize current consumption while maintaining voltage stability only when necessary.

The patent implements partial monitoring of the feedback voltage during sleep mode. The control circuit monitors the feedback voltage to determine if it exceeds a threshold value indicating sleep mode conditions, but does not continuously process all feedback signals. This partial action approach achieves sufficient detection accuracy to identify sleep mode entry while consuming minimal current, resolving the contradiction between measurement precision and power consumption.