Switching Regulator Clock Selection for Stable Light-Load Efficiency
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Solution Overview
Problem
Conventional switching regulators face instability in light load efficiency due to varying phase node voltages and inability to achieve zero voltage switching without adjusting operation frequency beyond acceptable ranges, particularly in applications requiring constant frequency.
Innovation Solution
A switching regulator with an operation clock signal generator circuit that generates test clock signals during a determination period, selects the minimum phase node voltage, and adjusts the operation clock signal to maintain constant frequency while improving light load efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the switching regulator operates at a single constant switching frequency, then the operation frequency remains stable, but the light load efficiency becomes unstable due to varying phase node voltages
Solution Approach 1:
The patent applies dynamics by making the switching frequency adjustable rather than fixed. The operation clock signal generator circuit dynamically selects from multiple test clock signals based on phase node voltage measurements, allowing the system to adapt its frequency to achieve zero voltage switching while maintaining overall frequency stability through controlled adjustment.
Solution Approach 2:
The patent changes the frequency parameter by generating multiple test clock signals with different frequencies and selectively applying them. The system measures phase node voltages at different frequencies and selects the optimal frequency that achieves minimum voltage (zero voltage switching), thereby improving light load efficiency while maintaining acceptable frequency stability.
2Loss of energy
If the operation frequency is adjusted to achieve zero voltage switching, then the light load efficiency improves, but the frequency may go beyond the acceptable range required by load circuits
Solution Approach 1:
The system dynamically adjusts frequency within a controlled range by testing multiple clock signals. The adjustment is not arbitrary but follows a systematic approach of generating test signals, measuring phase node voltages, and selecting the optimal frequency that achieves zero voltage switching while staying within acceptable limits for load circuits.
Solution Approach 2:
The patent employs feedback by measuring phase node voltages at different test frequencies and using this information to select the optimal operating frequency. The system continuously monitors the effect of frequency changes on phase node voltage and adjusts accordingly to achieve zero voltage switching without exceeding acceptable frequency ranges.
3Loss of energy
If multiple test clock signals are generated and evaluated, then the optimal frequency for zero voltage switching can be found, but the device complexity increases
Solution Approach 1:
The patent segments the clock signal generation into discrete testable components. Instead of continuously varying frequency, the system divides the frequency range into discrete test points using multiple test clock signals. This segmentation allows systematic evaluation of different frequencies while keeping the control logic manageable and the implementation practical.
Data Source
AI summary
A switching regulator includes: a power stage circuit; a control circuit; and an operation clock signal generator circuit configured to generate plural test clock signals during a clock determination period and generate an operation clock signal during a normal operation period. When the switching regulator operates during the clock determination period in a discontinuous conduction mode, the control circuit alternatingly generates plural PWM signals corresponding to the test clock signals generated by the operation clock signal generator circuit and an output voltage, wherein each PWM signal corresponds to one test clock signal, so that the power stage circuit generates corresponding phase node voltages at a phase node, wherein among the plural test clock signals, the operation clock signal generator circuit selects one test clock signal corresponding to a minimum phase node voltage as the operation clock signal during the normal operation period.