Switching Regulator Dynamic Deadtime Control

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Solution Overview

Problem

Switching regulators face efficiency losses due to improper deadtime management, leading to body diode conduction and reverse recovery issues, which can result in wasted power if deadtimes are too long or if both power FETs conduct simultaneously.

Innovation Solution

The solution involves controlling the operation of high side and low side switches in a switching regulator by using inductor current to charge and discharge an intermediate switching node when both switches are open, with programmable delays between transitions to optimize deadtimes, ensuring efficient operation by preventing shoot-through currents and minimizing power loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If deadtimes are made longer to prevent simultaneous conduction of power FETs, then shoot-through currents are reduced, but efficiency deteriorates due to body diode conduction and reverse recovery losses

Engineering Contradiction:
Improveprevention of shoot-through currentsVSAvoidpower loss from body diode conduction
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent implements dynamic deadtime adjustment where the deadtime period is not fixed but is continuously optimized based on operating conditions. The control circuit dynamically modifies the deadtime duration to balance between preventing shoot-through currents and minimizing body diode conduction losses, thereby resolving the contradiction between reliability and energy efficiency.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the deadtime parameter adaptively based on operating conditions such as load current and switching frequency. By adjusting this critical timing parameter, the system optimizes the trade-off between preventing simultaneous FET conduction (reliability) and minimizing energy losses from body diode operation (efficiency).

Inventive Principle:
Principle #35Parameter changes

2Loss of energy

If deadtimes are reduced to minimize body diode conduction losses, then efficiency improves, but simultaneous conduction of power FETs increases causing shoot-through currents

Engineering Contradiction:
Improvepower loss from body diode conductionVSAvoidsimultaneous conduction of power FETs
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent employs feedback mechanisms where the control circuit monitors operating conditions and adjusts the deadtime accordingly. This closed-loop control ensures that the deadtime is sufficient to prevent shoot-through currents while being minimized to reduce body diode conduction losses, dynamically resolving the contradiction between efficiency and reliability.

Inventive Principle:
Principle #23Feedback

3Device complexity

If fixed deadtime is used for simplicity, then device complexity is reduced, but efficiency deteriorates due to inability to optimize for varying operating conditions

Engineering Contradiction:
Improvecontrol circuit complexityVSAvoidpower loss from non-optimized deadtime
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The patent transitions from fixed deadtime to dynamic deadtime adjustment, where the control circuit adapts the deadtime duration based on real-time operating conditions. This dynamic approach optimizes efficiency across varying loads and frequencies while maintaining manageable circuit complexity through systematic control design.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9866104B2Circuits and methods for operating a switching regulator
Publication Date: 2018.01.09 GAZELLE SEMICONDUCTOR INC
  • US9866104B2 patent drawing
  • US9866104B2 patent drawing
  • US9866104B2 patent drawing

AI summary

The present disclosure includes circuits and methods for controlling the operation of a switching regulator. Closing and opening high side and low side switches may be controlled so that an inductor current may be used to charge and/or discharge an intermediate switching node when both switches are open. In one embodiment, delays between a low-to-high transition and a high-to-low transition of an AC stage may be cycled over multiple periods of a DC stage.