Multi-Channel Switching Regulator Frequency Segmentation
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Solution Overview
Problem
Multiple channel switching regulator systems face challenges in maintaining high input to output voltage ratios while keeping constant synchronized switching frequencies, leading to increased component size and output ripple due to minimum on-time restrictions and high voltage ratios.
Innovation Solution
The system employs individual constant synchronized switching frequencies for each switching regulator channel, using clock circuits to set distinct switching frequencies for each channel, allowing for optimized external component sizes and maximizing input to output voltage ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a single constant switching frequency is used for all channels, then system synchronization and noise control are improved, but component size increases and output ripple increases due to minimum on-time restrictions in high voltage ratio channels
Solution Approach 1:
The patent divides the system into multiple independent clock circuits, each dedicated to a specific switching regulator channel. Each clock circuit generates its own switching frequency independently, allowing channels with different voltage ratios to operate at optimized frequencies without being constrained by a single system-wide frequency limit.
Solution Approach 2:
The patent implements dynamic frequency allocation where each channel can operate at its optimal switching frequency based on its specific voltage conversion requirements. Channels with high input-to-output voltage ratios can run at lower frequencies to meet minimum on-time requirements, while other channels can operate at higher frequencies to minimize component size and output ripple.
2Stability of the object's composition
If a single constant switching frequency is used for all channels, then system synchronization is maintained, but output voltage ripple increases due to minimum on-time restrictions in high voltage ratio channels
Solution Approach 1:
The patent segments the clock generation function into separate clock circuits for each channel, allowing independent frequency optimization. This enables channels to operate at frequencies that minimize their specific output ripple characteristics while maintaining overall system functionality.
Solution Approach 2:
The patent changes the frequency parameter individually for each channel based on its specific voltage conversion ratio and ripple requirements. By allowing frequency to vary per channel rather than being fixed system-wide, each channel can be optimized to minimize its output voltage ripple while maintaining synchronization through coordinated clock generation.
3Volume of moving object
If switching frequency is reduced to accommodate minimum on-time requirements in high voltage ratio channels, then component size can be reduced, but system productivity and efficiency decrease
Solution Approach 1:
The patent implements dynamic frequency allocation where each channel operates at its optimal frequency for its specific voltage conversion task. High voltage ratio channels can use lower frequencies when needed, while other channels maintain higher frequencies for improved efficiency and reduced component size, thereby optimizing overall system productivity.
Solution Approach 2:
The patent enables independent frequency parameter optimization for each channel based on its specific operating conditions. This allows the system to maximize efficiency by having each channel operate at its peak performance frequency rather than being constrained by the lowest frequency requirement in the system.
Data Source
AI summary
Novel circuitry and methodology for operating a multiple channel switching regulator system to extend an input to output voltage ratio by setting individual constant switching frequencies to switching regulator channels. In the switching regulator system having at least first and second switching regulators, a first clock circuit supplies a first clock signal at a first clock frequency to define a switching frequency of one of the first and second switching regulators. A second clock circuit is synchronized to the first clock signal for producing a second clock signal at a second clock frequency different from the first clock frequency, to define a switching frequency of the other of the first and second switching regulators.