Switching Regulator Offset Comparison Circuit Ripple Reduction
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Solution Overview
Problem
The existing switching regulators experience an increase in ripple voltage during PFM operation due to response delays in the PFM comparison circuit, leading to unnecessary switching operations and inefficiencies.
Innovation Solution
Incorporating an offset into the input of the PFM comparison circuit for a given period to compensate for response delays, preventing unnecessary switching element operations during PFM operation by adjusting the error voltage comparison, thereby reducing ripple voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PFM comparison circuit operates without offset compensation, then the circuit structure remains simple, but response delays cause unnecessary switching operations and increased ripple voltage
Solution Approach 1:
The patent applies preliminary action by adding an offset voltage to the error voltage input of the PFM comparison circuit before the comparison operation. This offset is added in advance to compensate for the expected response delay, allowing the comparison to trigger the switching operation at the correct time rather than after the delay occurs. The offset cancellation unit then removes this offset after the comparison, ensuring accurate subsequent operations.
Solution Approach 2:
The patent changes the voltage parameter by introducing an offset voltage component to the error voltage signal. This parameter modification shifts the comparison threshold dynamically, allowing the PFM comparison circuit to account for its inherent response delay without requiring structural changes. The offset voltage adjusts the effective comparison point, compensating for the time delay in the comparison process.
2Object-generated harmful factors
If offset compensation is added to the PFM comparison circuit, then ripple voltage is reduced through timely switching operations, but the circuit structure becomes more complex
Solution Approach 1:
The offset voltage is added in advance to the error voltage before comparison, preemptively compensating for the response delay that would otherwise cause late switching operations. This preliminary adjustment ensures that the switching occurs at the optimal moment, minimizing ripple voltage generation in the output.
Solution Approach 2:
The offset voltage acts as an intermediary element between the error voltage and the PFM comparison operation. It mediates the timing discrepancy by shifting the comparison threshold, allowing the circuit to achieve accurate timing without directly modifying the core comparison mechanism or requiring complex timing circuits.
3Loss of energy
If the PFM comparison circuit has response delay, then the circuit operation is stable, but unnecessary switching operations occur increasing power loss
Solution Approach 1:
By adding the offset voltage in advance, the system compensates for the inevitable response delay time. This allows the comparison to be effectively performed at the correct moment, preventing unnecessary switching operations that would waste energy. The offset ensures that the switching occurs only when truly needed, eliminating redundant cycles.
Solution Approach 2:
The offset voltage applies a preliminary counteracting influence to the response delay effect. By shifting the comparison threshold in the opposite direction of the delay effect, it pre-compensates for the timing error, ensuring that the switching operation is triggered at the optimal time rather than after energy-wasting delays.
Data Source
AI summary
A switching regulator includes: an error amplification circuit configured to amplify a difference between a voltage based on the output voltage and a first reference voltage to output an error voltage; a PFM comparison circuit configured to compare the error voltage with a second reference voltage to output a comparison result signal at a first level or a second level, an offset being given to the error voltage for a given period in response to a change of the comparison result signal from the second level to the first level; an oscillation circuit configured to output a clock signal of a given frequency according to the first level of the comparison result signal, and to stop outputting the clock signal according to the second level of the comparison result signal; and a PWM conversion circuit configured to turn the switching element on at a prescribed pulse width.