Switching Regulator PFM Detector Clamping Error Voltage
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Solution Overview
Problem
Conventional switching regulators experience increased ripple voltage in PFM operation due to excessive switching of the PMOS transistor, caused by delayed timing in the phase compensation circuit, leading to inefficiencies in power conversion.
Innovation Solution
A switching regulator with a clamper and PFM detector that clamps the error voltage and detects the polarity of the error current, preventing excessive switching operations by controlling the oscillator's output signal, thereby reducing the ripple voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a phase compensation circuit is used to suppress oscillation of the negative feedback loop, then stability of the system is improved, but the timing of error voltage becomes delayed causing excessive switching operations in PFM mode
Solution Approach 1:
The patent segments the error voltage generation into two paths: a main path through the phase compensation circuit for stability, and a fast path directly from the error amplifier to the PFM detector for timely PFM detection. This segmentation allows the system to maintain stability while avoiding timing delays in PFM operation.
Solution Approach 2:
The patent introduces a buffer amplifier as an intermediary component that receives the error voltage from the error amplifier and provides it to the PFM detector. This buffer amplifier acts as a mediator that delivers the error voltage without the timing delay introduced by the phase compensation circuit, enabling timely PFM detection while maintaining system stability.
2Speed
If the oscillator continues to supply clock signals during PFM operation, then the switching element can respond quickly to load changes, but excessive switching operations occur increasing ripple voltage
Solution Approach 1:
The patent implements feedback through the PFM detector that monitors the error voltage and provides feedback to the oscillator to control clock signal supply. When the error voltage indicates PFM operation conditions, the feedback mechanism stops the oscillator from supplying clock signals, thereby preventing excessive switching operations and reducing ripple voltage while maintaining quick response capability when needed.
3Loss of energy
If PWM operation is used under large load current, then power conversion efficiency is maintained, but the error voltage becomes excessively large triggering unnecessary PFM operation
Solution Approach 1:
The patent applies local quality by using different processing for the error voltage in different operational contexts. The PFM detector specifically monitors the polarity and magnitude characteristics of the error voltage to distinguish between legitimate PFM conditions and situations where PWM operation should continue, ensuring accurate PFM detection while maintaining power conversion efficiency.
Data Source
AI summary
A switching regulator has an error amplifier supplying an error current, a phase compensation portion generating an error voltage, a clamper clamping the error voltage, a PFM detector supplying a comparison result signal of a first level or a comparison result signal of a second level based on the error current, an oscillator supplying a clock signal in response to the comparison result signal at the second level and fixing the clock signal in response to the comparison result signal at the first level, and a PWM converter turning on/off a switching element with a desired pulse width based on the error voltage and the output from the oscillator.