Switching Regulator Timer Circuit Light Load Power

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Solution Overview

Problem

Switching regulators face inefficiencies and high power consumption in light load modes due to the comparator's current consumption, leading to increased ripple voltage and reduced efficiency when load currents are low.

Innovation Solution

Incorporating a timer circuit that switches the comparator's operation to a low current consumption mode based on a count-up signal, allowing the switching regulator to reduce power consumption without compromising efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the comparator operates at normal current consumption, then the response speed is fast and delay is small, but the power consumption increases in light load mode

Engineering Contradiction:
Improvepower consumptionVSAvoiddelay
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The comparator dynamically switches between normal operation mode and low current consumption mode based on the timing signal from the timer circuit. During the first prescribed time period after power FET turn-on, the comparator operates at normal current for fast response. After this period, it switches to low current mode to reduce power consumption in light load conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The timer circuit generates periodic timing signals that control the comparator's operation mode. The comparator alternates between high-current normal operation during the initial period and low-current operation during subsequent periods, achieving periodic switching that balances response speed and power consumption.

Inventive Principle:
Principle #19Periodic action

2Use of energy by moving object

If the comparator current consumption is reduced, then the power consumption decreases in light load mode, but the delay becomes large and ripple voltage increases

Engineering Contradiction:
Improvecurrent consumptionVSAvoidripple voltage
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The timer circuit performs preliminary action by generating a timing signal that keeps the comparator in normal operation mode during the critical initial period after power FET turn-on. This ensures that the comparator operates at full performance during the most critical phase, preventing excessive delay and ripple voltage before switching to power-saving mode.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The timer circuit acts as an intermediary between the power FET control and the comparator operation. It monitors the power FET turn-on timing and controls the comparator's current consumption mode accordingly, mediating between the need for fast response and the need for low power consumption.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10284085B2Switching regulator
Publication Date: 2019.05.07 ABLIC INC
  • US10284085B2 patent drawing
  • US10284085B2 patent drawing
  • US10284085B2 patent drawing

AI summary

A switching regulator includes a comparator, an on-time control circuit, an R-S flip-flop circuit, and a timer circuit that outputs a count-up signal, where the comparator switches an operation current to a low current consumption mode in response to the count-up signal so as to reduce the operation current in a light load operating mode.