Switching System PWM Timing Shift for Current Detection Precision
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Solution Overview
Problem
In switching systems with multiple switching circuits, such as inverter circuits, precision current detection is compromised due to switching noise, especially when using a 1-shunt inverter circuit, as existing methods struggle to apply noise reduction techniques effectively, particularly in systems with a common shunt resistor for multiple phases.
Innovation Solution
The implementation of a switching system with first and second PWM timing generation circuits and AD conversion circuits, where one of the switching circuits is an inverter circuit with a common shunt resistor, adjusts the edge timings to ensure a predetermined interval between edge timings and AD conversion timings, enhancing current detection precision by synchronizing or shifting these timings to minimize noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If switching circuits operate simultaneously with fixed PWM cycles, then system coordination is simplified, but current detection precision deteriorates due to switching noise interference
Solution Approach 1:
The patent applies dynamics by making the PWM cycle adaptive rather than fixed. The control device dynamically adjusts the PWM cycle based on the switching timings of other switching circuits to ensure AD conversion occurs during noise-free intervals. This resolves the contradiction by allowing the system to maintain simple coordination through dynamic adaptation rather than rigid fixed cycles.
Solution Approach 2:
The patent changes the parameter of PWM cycle length dynamically. By adjusting the PWM cycle based on the switching timings of multiple switching circuits, the system ensures that AD conversion timing falls in intervals without switching noise. This parameter change enables both coordinated operation and high-current detection precision.
2Device complexity
If PWM cycles are set to the same or integral multiples, then timing coordination is simplified, but current detection precision deteriorates when switching noise occurs at sampling timing
Solution Approach 1:
The patent makes the PWM cycle dynamic rather than statically fixed to simple relationships. The control device calculates appropriate PWM cycles based on the actual switching timings of all switching circuits, enabling the system to maintain low complexity in coordination while avoiding noise interference at sampling points.
Solution Approach 2:
The patent employs feedback by having the control device monitor the switching timings of multiple switching circuits and adjust the PWM cycle accordingly. This feedback mechanism ensures that AD conversion timing is always positioned in noise-free intervals, resolving the contradiction between coordination simplicity and detection precision.
3Measurement precision
If switching timing is corrected to avoid noise interference, then current detection precision improves, but system complexity increases due to additional correction mechanisms
Solution Approach 1:
The patent applies universality by integrating the timing coordination and noise avoidance functions into a single PWM cycle determination process. The control device simultaneously performs multiple functions: coordinating PWM cycles across switching circuits and positioning AD conversion in noise-free intervals, without requiring separate correction mechanisms.
Solution Approach 2:
The control device performs self-service by autonomously determining appropriate PWM cycles based on the switching timings it monitors. The system self-adjusts to avoid noise interference through its own control logic, eliminating the need for external correction mechanisms and reducing overall system complexity.
Data Source
AI summary
An object of the invention is to improve precision of current detection in a switching system having plural switching circuits. A first PWM timing generation circuit generates an edge timing of a PWM signal by using a comparison value and a count value and drives a first switching circuit. A second PWM timing generation circuit generates an edge timing of a PWM signal of plural phases by using a comparison value and a count value and drives a second switching circuit. One of the switching circuits is an inverter circuit of a common shunt type in which a shunt resistor is provided commonly for plural phases. One of the PWM timing generation circuits shifts the generated edge timing so that an interval between an edge timing of one of the circuits and an AD conversion timing of the other becomes equal to or larger than a predetermined reference value.