Switching Transistor Gate Wiring Layer Separation for Parasitic Capacitance Reduction
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Solution Overview
Problem
In high-definition organic electroluminescence (EL) display devices, parasitic capacitance between adjacent wirings causes display unevenness due to coupling noise, which affects the uniformity of the display screen.
Innovation Solution
The gate wiring of the switching transistor is formed in a different wiring layer than that of other transistors, increasing the wiring interval and reducing parasitic capacitance, thereby suppressing the influence of coupling noise on the switching transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the gate wiring of the switching transistor is formed in the same wiring layer as other transistors, then the device complexity is reduced and manufacturing is easier, but parasitic capacitance between adjacent wirings increases causing display unevenness
Solution Approach 1:
The gate wiring of the switching transistor is formed in a different wiring layer (second wiring layer) compared to other transistors (first wiring layer), utilizing the vertical dimension to increase spacing between adjacent wirings. This layer separation reduces parasitic capacitance coupling between the switching transistor gate wiring and adjacent wirings, thereby suppressing display unevenness while maintaining reasonable device complexity through systematic multi-layer wiring design.
2Object-affected harmful factors
If the wiring interval between gate wirings is increased by forming them in different layers, then parasitic capacitance is reduced, but the device structure becomes more complex
Solution Approach 1:
The patent applies vertical layering to increase horizontal wiring spacing, forming the gate wiring of the switching transistor in a second wiring layer while other transistor gate wirings are in a first wiring layer. This dimensional transition effectively reduces parasitic capacitance between adjacent wirings by increasing their physical separation in the vertical dimension, accepting increased structural complexity as a necessary trade-off for achieving the required parasitic capacitance reduction in high-definition displays.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitance and minimizes display unevenness, enhancing the display quality by stabilizing the potential of the gate wiring of the switching transistor.
Implementation Method 1
parasitic capacitance generated between adjacent wirings cannot be disregarded
Data Source
AI summary
In a display device including: pixels including a light emitting unit and a plurality of transistors and two-dimensionally arranged in a matrix; and gate wirings of the plurality of transistors formed along a row direction of a pixel array, or an electronic device including the display device, among the plurality of transistors, a gate wiring of a switching transistor connected to an anode electrode of the light emitting unit is formed in a wiring layer different from a gate wiring of another transistor.