Switchless Deterministic Data Bus for Spacecraft Weight Reduction

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Solution Overview

Problem

Current data bus technologies, such as AFDX and IEEE 1394, either require heavy and power-intensive switches or lack deterministic timing, making them unsuitable for weight and power-sensitive applications like space vehicles, where a switchless network with guaranteed deterministic data transport is needed.

Innovation Solution

A dual switchless shared bandwidth data bus network with a deterministic transport layer that uses a pre-negotiated protocol for message scheduling and flow control, leveraging existing protocols like IEEE 1394b and ARINC 664 to ensure predictable bandwidth allocation and minimize weight and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If switches are used to interconnect end systems in AFDX networks, then deterministic data transport and bandwidth control are achieved, but weight and power consumption increase significantly

Engineering Contradiction:
Improvedeterministic data transportVSAvoidnetwork infrastructure weight
Core Design Contradiction:
ReliabilityVSWeight of moving object

Solution Approach 1:

The patent extracts and removes the switch components from the network architecture, transitioning from a switch-based AFDX network to a shared bus network. This elimination of switches directly reduces weight and power consumption while maintaining deterministic data transport through protocol-level scheduling mechanisms implemented in software/firmware at the end systems.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a deterministic transport protocol as an intermediary layer that mediates data transmission between end systems on the shared bus. This protocol layer provides the deterministic scheduling and bandwidth control functions previously performed by hardware switches, enabling switchless operation while preserving reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If switches are used to interconnect end systems in AFDX networks, then deterministic data transport and bandwidth control are achieved, but power consumption and EPGDS sizing increase

Engineering Contradiction:
Improvedeterministic data transportVSAvoidnetwork infrastructure power consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent removes power-consuming switch hardware from the network, eliminating their energy requirements. The deterministic scheduling functions are migrated to software/firmware implementations at end systems, which consume significantly less power than dedicated switch hardware, thereby reducing overall network power consumption and EPGDS sizing requirements.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Each end system independently performs scheduling and bandwidth control functions through the deterministic transport protocol, eliminating the need for external power-intensive switch infrastructure. The systems self-manage their data transmission timing and bandwidth allocation without requiring centralized power-hungry switching hardware.

Inventive Principle:
Principle #25Self-service

3Weight of moving object

If CSMA/CD shared bus network is used instead of switched Ethernet, then weight and power are reduced, but deterministic timing and guaranteed message transmission within predetermined time are lost

Engineering Contradiction:
Improvenetwork infrastructure weightVSAvoiddeterministic timing
Core Design Contradiction:
Weight of moving objectVSReliability

Solution Approach 1:

The patent implements preliminary scheduling of data transmissions through the deterministic transport protocol, where transmission slots and bandwidth allocations are predetermined and negotiated before actual data transfer. This pre-planning of transmission timing eliminates the random access nature of CSMA/CD, ensuring deterministic timing while maintaining the lightweight shared bus architecture.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs periodic transmission cycles and time-division multiplexing in the deterministic transport protocol, where each end system is allocated specific time slots for data transmission. This periodic structure replaces the collision-based random access of CSMA/CD, providing guaranteed bandwidth and deterministic timing while preserving the shared bus topology's weight advantages.

Inventive Principle:
Principle #19Periodic action

4Speed

If asynchronous stream mode of IEEE 1394 is used for IP over IEEE 1394, then high-speed communication is achieved, but latency control and deterministic timing are not provided

Engineering Contradiction:
Improvedata transmission speedVSAvoidlatency control
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent dynamically adjusts transmission parameters and scheduling decisions based on real-time network conditions and priority levels through the deterministic transport protocol. This dynamic control mechanism allocates bandwidth and timing resources adaptively while maintaining deterministic latency bounds, overcoming the static asynchronous stream mode's inability to provide latency control while preserving high-speed communication capabilities.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8451860B2Low-weight hybrid deterministic highspeed data bus
Publication Date: 2013.05.28 THE BOEING CO
  • US8451860B2 patent drawing
  • US8451860B2 patent drawing
  • US8451860B2 patent drawing

AI summary

Switchless deterministic data bus networks and interfaces are disclosed. In one embodiment, a network includes a switchless shared bandwidth data bus; a plurality of nodes in communication with the shared bandwidth data bus; and a deterministic transport layer hosted on each node of the plurality of nodes, the deterministic transport layer providing message scheduling and flow control, the message scheduling using a bandwidth allocation and physical layer prioritization access protocol for scheduling a packet. An embodiment of an interface includes a packager that packages data received from the host processor into packets compatible with a switchless shared bandwidth network; an un-packager that un-packs data packets received from the network, removes payload data, and transmits the payload data to the host processor; and a deterministic bus scheduler and controller that controls and schedules the transmission of data over the switchless shared bandwidth network such that the network is a deterministic network.