Switchless Semiconductor Pooled Memory Using Direct SoC Connections

The patent extracts and removes the CXL switch from the memory access path. Instead of routing all memory traffic through a centralized switch, the system directly connects processors to memory modules attached to different SoCs, eliminating the switch-induced latency while maintaining pooled memory functionality through inter-SoC communication.

The system segments the memory access paths by allowing each SoC to directly manage its attached memory modules while enabling cross-SoC access. This segmentation creates multiple parallel access paths rather than a single centralized path, reducing latency by allowing direct access without switch arbitration.

The patent removes the power-consuming CXL switch from the architecture. Memory sharing is achieved through direct connections between processors and memory modules attached to different SoCs, eliminating the continuous power consumption associated with switch operation while maintaining the ability to share memory across processors.

Each SoC independently manages its attached memory modules, performing memory control functions locally without requiring a centralized switch. This self-service approach reduces overall system power consumption by eliminating the need for a dedicated switching component while maintaining memory sharing capabilities.

The patent extracts and eliminates the CXL switch component from the system architecture. Pooled memory functionality is achieved through the existing inter-SoC communication infrastructure, removing the need for expensive switching hardware and reducing overall system cost while maintaining memory pooling capabilities.

The system uses the existing universal inter-SoC communication interface for multiple purposes: both for processor-to-processor communication and for memory access across SoCs. This multi-functionality eliminates the need for dedicated memory switching hardware, reducing system cost while maintaining pooled memory capability.