Swizzle Circuitry Endian Conversion Segmentation
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Solution Overview
Problem
Existing data processing apparatuses face complexity and timing constraints due to the need for swizzle circuitry to handle data values in various endian formats, leading to increased propagation delay and reduced processing speed.
Innovation Solution
The implementation of swizzle circuitry that performs endian conversion by assuming a predetermined data value size, with an additional reordering operation in a subsequent clock cycle for data values of different sizes, optimizing the circuitry to reduce complexity and improve speed for the majority of data values handled.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If complex swizzle circuitry is provided to handle data values of various different sizes, then the data processing apparatus can perform endian conversion for all data sizes, but the complexity of the swizzle circuitry increases and propagation delay increases
Solution Approach 1:
The patent divides the endian conversion process into two separate circuit stages: first swizzle circuitry that performs conversion assuming a predetermined data size, and second swizzle circuitry that performs additional conversion for data values of different sizes. This segmentation allows the first circuit to be simpler and faster, while the second circuit handles the remaining cases.
Solution Approach 2:
The first swizzle circuitry performs preliminary endian conversion on all data values assuming they are of the predetermined size. This preliminary action completes the conversion for the majority of cases quickly, and only requires the second circuit to handle corrections for exceptional cases where the actual size differs from the assumed size.
2Adaptability or versatility
If complex swizzle circuitry with many multiplexers is provided to handle various data sizes, then all data value sizes can be accommodated, but the critical path delay increases and processing speed decreases
Solution Approach 1:
The conversion path is segmented into two stages with different levels of complexity. The first stage uses simpler circuitry optimized for speed that handles the common case of predetermined size data values, while the second stage handles less common cases. This segmentation creates a faster critical path for the majority of operations.
Solution Approach 2:
Different levels of conversion complexity are applied locally based on the actual data size. The first swizzle circuitry provides full conversion capability for the predetermined size, while the second swizzle circuitry provides additional conversion only when needed for different sizes. This local differentiation optimizes overall speed without sacrificing versatility.
3Reliability
If swizzle circuitry is placed on the critical path to perform endian conversion, then data can be converted between endian formats, but the complexity of the critical path increases and limits the operating speed
Solution Approach 1:
The critical path is segmented to include only the first swizzle circuitry which has reduced complexity. The second swizzle circuitry operates in parallel or in a non-critical path, performing additional conversions only when needed. This segmentation removes excessive complexity from the critical path while maintaining full conversion capability.
Solution Approach 2:
The first swizzle circuitry performs preliminary endian conversion on the critical path, providing the necessary format conversion for the majority of cases. This preliminary action satisfies the reliability requirement for endian conversion while keeping the critical path complexity low, as the second circuit operates outside or after the critical path for exceptional cases.
Data Source
AI summary
A data processing apparatus and method are provided for converting data values from a first endian format to a second endian format. Swizzle circuitry is provided for receiving a block of data containing at least one data value, and for converting each data value from the first endian format to the second endian format. The swizzle circuitry comprises first swizzle circuitry for performing a re-ordering operation on the block of data assuming the at least one data value contained therein is of a first size, in order to produce re-ordered data. Second swizzle circuitry is provided which is responsive to an indication that the at least one data value is of a size different to the first size to perform an additional re-ordering operation on the re-ordered data having regard to the size of the at least one data value in order to convert each data value to the second endian format.